1NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.
2
3Required properties:
4- compatible : For Tegra20, must contain "nvidia,tegra20-efuse".  For Tegra30,
5  must contain "nvidia,tegra30-efuse".  For Tegra114, must contain
6  "nvidia,tegra114-efuse".  For Tegra124, must contain "nvidia,tegra124-efuse".
7  For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse".
8  For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain
9  "nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse".
10  For Tegra234 must contain "nvidia,tegra234-efuse".
11  Details:
12  nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
13	due to a hardware bug. Tegra20 also lacks certain information which is
14	available in later generations such as fab code, lot code, wafer id,..
15  nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse:
16	The differences between these SoCs are the size of the efuse array,
17	the location of the spare (OEM programmable) bits and the location of
18	the speedo data.
19- reg: Should contain 1 entry: the entry gives the physical address and length
20       of the fuse registers.
21- clocks: Must contain an entry for each entry in clock-names.
22  See ../clocks/clock-bindings.txt for details.
23- clock-names: Must include the following entries:
24  - fuse
25- resets: Must contain an entry for each entry in reset-names.
26  See ../reset/reset.txt for details.
27- reset-names: Must include the following entries:
28 - fuse
29
30Example:
31
32	fuse@7000f800 {
33		compatible = "nvidia,tegra20-efuse";
34		reg = <0x7000f800 0x400>,
35		      <0x70000000 0x400>;
36		clocks = <&tegra_car TEGRA20_CLK_FUSE>;
37		clock-names = "fuse";
38		resets = <&tegra_car 39>;
39		reset-names = "fuse";
40	};
41
42
43