1NVIDIA Tegra Video Decoder Engine 2 3Required properties: 4- compatible : Must contain one of the following values: 5 - "nvidia,tegra20-vde" 6 - "nvidia,tegra30-vde" 7 - "nvidia,tegra114-vde" 8 - "nvidia,tegra124-vde" 9 - "nvidia,tegra132-vde" 10- reg : Must contain an entry for each entry in reg-names. 11- reg-names : Must include the following entries: 12 - sxe 13 - bsev 14 - mbe 15 - ppe 16 - mce 17 - tfe 18 - ppb 19 - vdma 20 - frameid 21- iram : Must contain phandle to the mmio-sram device node that represents 22 IRAM region used by VDE. 23- interrupts : Must contain an entry for each entry in interrupt-names. 24- interrupt-names : Must include the following entries: 25 - sync-token 26 - bsev 27 - sxe 28- clocks : Must include the following entries: 29 - vde 30- resets : Must contain an entry for each entry in reset-names. 31- reset-names : Should include the following entries: 32 - vde 33 34Optional properties: 35- resets : Must contain an entry for each entry in reset-names. 36- reset-names : Must include the following entries: 37 - mc 38- iommus: Must contain phandle to the IOMMU device node. 39 40Example: 41 42video-codec@6001a000 { 43 compatible = "nvidia,tegra20-vde"; 44 reg = <0x6001a000 0x1000 /* Syntax Engine */ 45 0x6001b000 0x1000 /* Video Bitstream Engine */ 46 0x6001c000 0x100 /* Macroblock Engine */ 47 0x6001c200 0x100 /* Post-processing Engine */ 48 0x6001c400 0x100 /* Motion Compensation Engine */ 49 0x6001c600 0x100 /* Transform Engine */ 50 0x6001c800 0x100 /* Pixel prediction block */ 51 0x6001ca00 0x100 /* Video DMA */ 52 0x6001d800 0x300 /* Video frame controls */>; 53 reg-names = "sxe", "bsev", "mbe", "ppe", "mce", 54 "tfe", "ppb", "vdma", "frameid"; 55 iram = <&vde_pool>; /* IRAM region */ 56 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ 57 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ 58 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ 59 interrupt-names = "sync-token", "bsev", "sxe"; 60 clocks = <&tegra_car TEGRA20_CLK_VDE>; 61 reset-names = "vde", "mc"; 62 resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; 63 iommus = <&mc TEGRA_SWGROUP_VDE>; 64}; 65