1* Aspeed Firmware Memory controller
2* Aspeed SPI Flash Memory Controller
3
4The Firmware Memory Controller in the Aspeed AST2500 SoC supports
5three chip selects, two of which are always of SPI type and the third
6can be SPI or NOR type flash. These bindings only describe SPI.
7
8The two SPI flash memory controllers in the AST2500 each support two
9chip selects.
10
11Required properties:
12  - compatible : Should be one of
13	"aspeed,ast2400-fmc" for the AST2400 Firmware Memory Controller
14	"aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller
15	"aspeed,ast2500-fmc" for the AST2500 Firmware Memory Controller
16	"aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers
17
18  - reg : the first contains the control register location and length,
19          the second contains the memory window mapping address and length
20  - #address-cells : must be 1 corresponding to chip select child binding
21  - #size-cells : must be 0 corresponding to chip select child binding
22
23Optional properties:
24  - interrupts : Should contain the interrupt for the dma device if an
25    FMC
26
27The child nodes are the SPI flash modules which must have a compatible
28property as specified in bindings/mtd/jedec,spi-nor.txt
29
30Optionally, the child node can contain properties for SPI mode (may be
31ignored):
32  - spi-max-frequency - max frequency of spi bus
33
34
35Example:
36fmc: fmc@1e620000 {
37	compatible = "aspeed,ast2500-fmc";
38	reg = < 0x1e620000 0x94
39		0x20000000 0x02000000 >;
40	#address-cells = <1>;
41	#size-cells = <0>;
42	interrupts = <19>;
43	flash@0 {
44		reg = < 0 >;
45		compatible = "jedec,spi-nor";
46		/* spi-max-frequency = <>; */
47		/* m25p,fast-read; */
48		#address-cells = <1>;
49		#size-cells = <1>;
50	};
51};
52