1* Qualcomm PCI express root complex 2 3- compatible: 4 Usage: required 5 Value type: <stringlist> 6 Definition: Value should contain 7 - "qcom,pcie-ipq8064" for ipq8064 8 - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065 9 - "qcom,pcie-apq8064" for apq8064 10 - "qcom,pcie-apq8084" for apq8084 11 - "qcom,pcie-msm8996" for msm8996 or apq8096 12 - "qcom,pcie-ipq4019" for ipq4019 13 - "qcom,pcie-ipq8074" for ipq8074 14 - "qcom,pcie-qcs404" for qcs404 15 - "qcom,pcie-sc8180x" for sc8180x 16 - "qcom,pcie-sdm845" for sdm845 17 - "qcom,pcie-sm8250" for sm8250 18 - "qcom,pcie-ipq6018" for ipq6018 19 20- reg: 21 Usage: required 22 Value type: <prop-encoded-array> 23 Definition: Register ranges as listed in the reg-names property 24 25- reg-names: 26 Usage: required 27 Value type: <stringlist> 28 Definition: Must include the following entries 29 - "parf" Qualcomm specific registers 30 - "dbi" DesignWare PCIe registers 31 - "elbi" External local bus interface registers 32 - "config" PCIe configuration space 33 - "atu" ATU address space (optional) 34 35- device_type: 36 Usage: required 37 Value type: <string> 38 Definition: Should be "pci". As specified in snps,dw-pcie.yaml 39 40- #address-cells: 41 Usage: required 42 Value type: <u32> 43 Definition: Should be 3. As specified in snps,dw-pcie.yaml 44 45- #size-cells: 46 Usage: required 47 Value type: <u32> 48 Definition: Should be 2. As specified in snps,dw-pcie.yaml 49 50- ranges: 51 Usage: required 52 Value type: <prop-encoded-array> 53 Definition: As specified in snps,dw-pcie.yaml 54 55- interrupts: 56 Usage: required 57 Value type: <prop-encoded-array> 58 Definition: MSI interrupt 59 60- interrupt-names: 61 Usage: required 62 Value type: <stringlist> 63 Definition: Should contain "msi" 64 65- #interrupt-cells: 66 Usage: required 67 Value type: <u32> 68 Definition: Should be 1. As specified in snps,dw-pcie.yaml 69 70- interrupt-map-mask: 71 Usage: required 72 Value type: <prop-encoded-array> 73 Definition: As specified in snps,dw-pcie.yaml 74 75- interrupt-map: 76 Usage: required 77 Value type: <prop-encoded-array> 78 Definition: As specified in snps,dw-pcie.yaml 79 80- clocks: 81 Usage: required 82 Value type: <prop-encoded-array> 83 Definition: List of phandle and clock specifier pairs as listed 84 in clock-names property 85 86- clock-names: 87 Usage: required 88 Value type: <stringlist> 89 Definition: Should contain the following entries 90 - "iface" Configuration AHB clock 91 92- clock-names: 93 Usage: required for ipq/apq8064 94 Value type: <stringlist> 95 Definition: Should contain the following entries 96 - "core" Clocks the pcie hw block 97 - "phy" Clocks the pcie PHY block 98 - "aux" Clocks the pcie AUX block 99 - "ref" Clocks the pcie ref block 100- clock-names: 101 Usage: required for apq8084/ipq4019 102 Value type: <stringlist> 103 Definition: Should contain the following entries 104 - "aux" Auxiliary (AUX) clock 105 - "bus_master" Master AXI clock 106 - "bus_slave" Slave AXI clock 107 108- clock-names: 109 Usage: required for msm8996/apq8096 110 Value type: <stringlist> 111 Definition: Should contain the following entries 112 - "pipe" Pipe Clock driving internal logic 113 - "aux" Auxiliary (AUX) clock 114 - "cfg" Configuration clock 115 - "bus_master" Master AXI clock 116 - "bus_slave" Slave AXI clock 117 118- clock-names: 119 Usage: required for ipq8074 120 Value type: <stringlist> 121 Definition: Should contain the following entries 122 - "iface" PCIe to SysNOC BIU clock 123 - "axi_m" AXI Master clock 124 - "axi_s" AXI Slave clock 125 - "ahb" AHB clock 126 - "aux" Auxiliary clock 127 128- clock-names: 129 Usage: required for ipq6018 130 Value type: <stringlist> 131 Definition: Should contain the following entries 132 - "iface" PCIe to SysNOC BIU clock 133 - "axi_m" AXI Master clock 134 - "axi_s" AXI Slave clock 135 - "axi_bridge" AXI bridge clock 136 - "rchng" 137 138- clock-names: 139 Usage: required for qcs404 140 Value type: <stringlist> 141 Definition: Should contain the following entries 142 - "iface" AHB clock 143 - "aux" Auxiliary clock 144 - "master_bus" AXI Master clock 145 - "slave_bus" AXI Slave clock 146 147- clock-names: 148 Usage: required for sdm845 149 Value type: <stringlist> 150 Definition: Should contain the following entries 151 - "aux" Auxiliary clock 152 - "cfg" Configuration clock 153 - "bus_master" Master AXI clock 154 - "bus_slave" Slave AXI clock 155 - "slave_q2a" Slave Q2A clock 156 - "tbu" PCIe TBU clock 157 - "pipe" PIPE clock 158 159- clock-names: 160 Usage: required for sc8180x and sm8250 161 Value type: <stringlist> 162 Definition: Should contain the following entries 163 - "aux" Auxiliary clock 164 - "cfg" Configuration clock 165 - "bus_master" Master AXI clock 166 - "bus_slave" Slave AXI clock 167 - "slave_q2a" Slave Q2A clock 168 - "tbu" PCIe TBU clock 169 - "ddrss_sf_tbu" PCIe SF TBU clock 170 - "pipe" PIPE clock 171 172- resets: 173 Usage: required 174 Value type: <prop-encoded-array> 175 Definition: List of phandle and reset specifier pairs as listed 176 in reset-names property 177 178- reset-names: 179 Usage: required for ipq/apq8064 180 Value type: <stringlist> 181 Definition: Should contain the following entries 182 - "axi" AXI reset 183 - "ahb" AHB reset 184 - "por" POR reset 185 - "pci" PCI reset 186 - "phy" PHY reset 187 188- reset-names: 189 Usage: required for apq8084 190 Value type: <stringlist> 191 Definition: Should contain the following entries 192 - "core" Core reset 193 194- reset-names: 195 Usage: required for ipq/apq8064 196 Value type: <stringlist> 197 Definition: Should contain the following entries 198 - "axi_m" AXI master reset 199 - "axi_s" AXI slave reset 200 - "pipe" PIPE reset 201 - "axi_m_vmid" VMID reset 202 - "axi_s_xpu" XPU reset 203 - "parf" PARF reset 204 - "phy" PHY reset 205 - "axi_m_sticky" AXI sticky reset 206 - "pipe_sticky" PIPE sticky reset 207 - "pwr" PWR reset 208 - "ahb" AHB reset 209 - "phy_ahb" PHY AHB reset 210 - "ext" EXT reset 211 212- reset-names: 213 Usage: required for ipq8074 214 Value type: <stringlist> 215 Definition: Should contain the following entries 216 - "pipe" PIPE reset 217 - "sleep" Sleep reset 218 - "sticky" Core Sticky reset 219 - "axi_m" AXI Master reset 220 - "axi_s" AXI Slave reset 221 - "ahb" AHB Reset 222 - "axi_m_sticky" AXI Master Sticky reset 223 224- reset-names: 225 Usage: required for ipq6018 226 Value type: <stringlist> 227 Definition: Should contain the following entries 228 - "pipe" PIPE reset 229 - "sleep" Sleep reset 230 - "sticky" Core Sticky reset 231 - "axi_m" AXI Master reset 232 - "axi_s" AXI Slave reset 233 - "ahb" AHB Reset 234 - "axi_m_sticky" AXI Master Sticky reset 235 - "axi_s_sticky" AXI Slave Sticky reset 236 237- reset-names: 238 Usage: required for qcs404 239 Value type: <stringlist> 240 Definition: Should contain the following entries 241 - "axi_m" AXI Master reset 242 - "axi_s" AXI Slave reset 243 - "axi_m_sticky" AXI Master Sticky reset 244 - "pipe_sticky" PIPE sticky reset 245 - "pwr" PWR reset 246 - "ahb" AHB reset 247 248- reset-names: 249 Usage: required for sc8180x, sdm845 and sm8250 250 Value type: <stringlist> 251 Definition: Should contain the following entries 252 - "pci" PCIe core reset 253 254- power-domains: 255 Usage: required for apq8084 and msm8996/apq8096 256 Value type: <prop-encoded-array> 257 Definition: A phandle and power domain specifier pair to the 258 power domain which is responsible for collapsing 259 and restoring power to the peripheral 260 261- vdda-supply: 262 Usage: required 263 Value type: <phandle> 264 Definition: A phandle to the core analog power supply 265 266- vdda_phy-supply: 267 Usage: required for ipq/apq8064 268 Value type: <phandle> 269 Definition: A phandle to the analog power supply for PHY 270 271- vdda_refclk-supply: 272 Usage: required for ipq/apq8064 273 Value type: <phandle> 274 Definition: A phandle to the analog power supply for IC which generates 275 reference clock 276- vddpe-3v3-supply: 277 Usage: optional 278 Value type: <phandle> 279 Definition: A phandle to the PCIe endpoint power supply 280 281- phys: 282 Usage: required for apq8084 and qcs404 283 Value type: <phandle> 284 Definition: List of phandle(s) as listed in phy-names property 285 286- phy-names: 287 Usage: required for apq8084 and qcs404 288 Value type: <stringlist> 289 Definition: Should contain "pciephy" 290 291- <name>-gpios: 292 Usage: optional 293 Value type: <prop-encoded-array> 294 Definition: List of phandle and GPIO specifier pairs. Should contain 295 - "perst-gpios" PCIe endpoint reset signal line 296 - "wake-gpios" PCIe endpoint wake signal line 297 298* Example for ipq/apq8064 299 pcie@1b500000 { 300 compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie"; 301 reg = <0x1b500000 0x1000 302 0x1b502000 0x80 303 0x1b600000 0x100 304 0x0ff00000 0x100000>; 305 reg-names = "dbi", "elbi", "parf", "config"; 306 device_type = "pci"; 307 linux,pci-domain = <0>; 308 bus-range = <0x00 0xff>; 309 num-lanes = <1>; 310 #address-cells = <3>; 311 #size-cells = <2>; 312 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */ 313 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */ 314 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>; 315 interrupt-names = "msi"; 316 #interrupt-cells = <1>; 317 interrupt-map-mask = <0 0 0 0x7>; 318 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 319 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 320 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 321 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 322 clocks = <&gcc PCIE_A_CLK>, 323 <&gcc PCIE_H_CLK>, 324 <&gcc PCIE_PHY_CLK>, 325 <&gcc PCIE_AUX_CLK>, 326 <&gcc PCIE_ALT_REF_CLK>; 327 clock-names = "core", "iface", "phy", "aux", "ref"; 328 resets = <&gcc PCIE_ACLK_RESET>, 329 <&gcc PCIE_HCLK_RESET>, 330 <&gcc PCIE_POR_RESET>, 331 <&gcc PCIE_PCI_RESET>, 332 <&gcc PCIE_PHY_RESET>, 333 <&gcc PCIE_EXT_RESET>; 334 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 335 pinctrl-0 = <&pcie_pins_default>; 336 pinctrl-names = "default"; 337 }; 338 339* Example for apq8084 340 pcie0@fc520000 { 341 compatible = "qcom,pcie-apq8084", "snps,dw-pcie"; 342 reg = <0xfc520000 0x2000>, 343 <0xff000000 0x1000>, 344 <0xff001000 0x1000>, 345 <0xff002000 0x2000>; 346 reg-names = "parf", "dbi", "elbi", "config"; 347 device_type = "pci"; 348 linux,pci-domain = <0>; 349 bus-range = <0x00 0xff>; 350 num-lanes = <1>; 351 #address-cells = <3>; 352 #size-cells = <2>; 353 ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */ 354 0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */ 355 interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>; 356 interrupt-names = "msi"; 357 #interrupt-cells = <1>; 358 interrupt-map-mask = <0 0 0 0x7>; 359 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 360 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 361 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 362 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 363 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 364 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 365 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 366 <&gcc GCC_PCIE_0_AUX_CLK>; 367 clock-names = "iface", "master_bus", "slave_bus", "aux"; 368 resets = <&gcc GCC_PCIE_0_BCR>; 369 reset-names = "core"; 370 power-domains = <&gcc PCIE0_GDSC>; 371 vdda-supply = <&pma8084_l3>; 372 phys = <&pciephy0>; 373 phy-names = "pciephy"; 374 perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>; 375 pinctrl-0 = <&pcie0_pins_default>; 376 pinctrl-names = "default"; 377 }; 378