1Socionext UniPhier PCIe host controller bindings
2
3This describes the devicetree bindings for PCIe host controller implemented
4on Socionext UniPhier SoCs.
5
6UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core.
7It shares common functions with the PCIe DesignWare core driver and inherits
8common properties defined in
9Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
10
11Required properties:
12- compatible: Should be "socionext,uniphier-pcie".
13- reg: Specifies offset and length of the register set for the device.
14	According to the reg-names, appropriate register sets are required.
15- reg-names: Must include the following entries:
16    "dbi"    - controller configuration registers
17    "link"   - SoC-specific glue layer registers
18    "config" - PCIe configuration space
19    "atu"    - iATU registers for DWC version 4.80 or later
20- clocks: A phandle to the clock gate for PCIe glue layer including
21	the host controller.
22- resets: A phandle to the reset line for PCIe glue layer including
23	the host controller.
24- interrupts: A list of interrupt specifiers. According to the
25	interrupt-names, appropriate interrupts are required.
26- interrupt-names: Must include the following entries:
27    "dma" - DMA interrupt
28    "msi" - MSI interrupt
29
30Optional properties:
31- phys: A phandle to generic PCIe PHY. According to the phy-names, appropriate
32	phys are required.
33- phy-names: Must be "pcie-phy".
34
35Required sub-node:
36- legacy-interrupt-controller: Specifies interrupt controller for legacy PCI
37	interrupts.
38
39Required properties for legacy-interrupt-controller:
40- interrupt-controller: identifies the node as an interrupt controller.
41- #interrupt-cells: specifies the number of cells needed to encode an
42	interrupt source. The value must be 1.
43- interrupt-parent: Phandle to the parent interrupt controller.
44- interrupts: An interrupt specifier for legacy interrupt.
45
46Example:
47
48	pcie: pcie@66000000 {
49		compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
50		status = "disabled";
51		reg-names = "dbi", "link", "config";
52		reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
53		      <0x2fff0000 0x10000>;
54		#address-cells = <3>;
55		#size-cells = <2>;
56		clocks = <&sys_clk 24>;
57		resets = <&sys_rst 24>;
58		num-lanes = <1>;
59		num-viewport = <1>;
60		bus-range = <0x0 0xff>;
61		device_type = "pci";
62		ranges =
63		/* downstream I/O */
64			<0x81000000 0 0x00000000  0x2ffe0000  0 0x00010000
65		/* non-prefetchable memory */
66			 0x82000000 0 0x00000000  0x20000000  0 0x0ffe0000>;
67		#interrupt-cells = <1>;
68		interrupt-names = "dma", "msi";
69		interrupts = <0 224 4>, <0 225 4>;
70		interrupt-map-mask = <0 0 0  7>;
71		interrupt-map = <0 0 0  1  &pcie_intc 0>,	/* INTA */
72				<0 0 0  2  &pcie_intc 1>,	/* INTB */
73				<0 0 0  3  &pcie_intc 2>,	/* INTC */
74				<0 0 0  4  &pcie_intc 3>;	/* INTD */
75
76		pcie_intc: legacy-interrupt-controller {
77			interrupt-controller;
78			#interrupt-cells = <1>;
79			interrupt-parent = <&gic>;
80			interrupts = <0 226 4>;
81		};
82	};
83