1V3 Semiconductor V360 EPC PCI bridge
2
3This bridge is found in the ARM Integrator/AP (Application Platform)
4
5Required properties:
6- compatible: should be one of:
7  "v3,v360epc-pci"
8  "arm,integrator-ap-pci", "v3,v360epc-pci"
9- reg: should contain two register areas:
10  first the base address of the V3 host bridge controller, 64KB
11  second the configuration area register space, 16MB
12- interrupts: should contain a reference to the V3 error interrupt
13  as routed on the system.
14- bus-range: see pci.txt
15- ranges: this follows the standard PCI bindings in the IEEE Std
16  1275-1994 (see pci.txt) with the following restriction:
17  - The non-prefetchable and prefetchable memory windows must
18    each be exactly 256MB (0x10000000) in size.
19  - The prefetchable memory window must be immediately adjacent
20    to the non-prefetcable memory window
21- dma-ranges: three ranges for the inbound memory region. The ranges must
22  be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB,
23  64MB, 128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked
24  as pre-fetchable. Two ranges are supported by the hardware.
25
26Integrator-specific required properties:
27- syscon: should contain a link to the syscon device node, since
28  on the Integrator, some registers in the syscon are required to
29  operate the V3 host bridge.
30
31Example:
32
33pci: pciv3@62000000 {
34	compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
35	#interrupt-cells = <1>;
36	#size-cells = <2>;
37	#address-cells = <3>;
38	reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
39	interrupt-parent = <&pic>;
40	interrupts = <17>; /* Bus error IRQ */
41	clocks = <&pciclk>;
42	bus-range = <0x00 0xff>;
43	ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */
44		0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */
45		0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
46		0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
47		0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
48		0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
49	dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
50		0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */
51		0x02000000 0 0x80000000 /* Core module alias memory */
52		0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */
53	interrupt-map-mask = <0xf800 0 0 0x7>;
54	interrupt-map = <
55	/* IDSEL 9 */
56	0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
57	0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
58	0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
59	0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
60	/* IDSEL 10 */
61	0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
62	0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
63	0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
64	0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
65	/* IDSEL 11 */
66	0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
67	0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
68	0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
69	0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
70	/* IDSEL 12 */
71	0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
72	0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
73	0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
74	0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
75	>;
76};
77