1* ROCKCHIP type-c PHY
2---------------------
3
4Required properties:
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
8   register files"
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
12		    <&cru SCLK_UPHY1_TCPDCORE>;
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
15 - reset-names : string reset name, must be:
16		 "uphy", "uphy-pipe", "uphy-tcphy"
17
18Optional properties:
19 - extcon : extcon specifier for the Power Delivery
20
21Required nodes : a sub-node is required for each port the phy provides.
22		 The sub-node name is used to identify dp or usb3 port,
23		 and shall be the following entries:
24	* "dp-port" : the name of DP port.
25	* "usb3-port" : the name of USB3 port.
26
27Required properties (port (child) node):
28- #phy-cells : must be 0, See ./phy-bindings.txt for details.
29
30Deprecated properties, do not use in new device tree sources, these
31properties are determined by the compatible value:
32 - rockchip,typec-conn-dir
33 - rockchip,usb3tousb2-en
34 - rockchip,external-psm
35 - rockchip,pipe-status
36
37Example:
38	tcphy0: phy@ff7c0000 {
39		compatible = "rockchip,rk3399-typec-phy";
40		reg = <0x0 0xff7c0000 0x0 0x40000>;
41		rockchip,grf = <&grf>;
42		extcon = <&fusb0>;
43		clocks = <&cru SCLK_UPHY0_TCPDCORE>,
44			 <&cru SCLK_UPHY0_TCPDPHY_REF>;
45		clock-names = "tcpdcore", "tcpdphy-ref";
46		assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
47		assigned-clock-rates = <50000000>;
48		resets = <&cru SRST_UPHY0>,
49			 <&cru SRST_UPHY0_PIPE_L00>,
50			 <&cru SRST_P_UPHY0_TCPHY>;
51		reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
52
53		tcphy0_dp: dp-port {
54			#phy-cells = <0>;
55		};
56
57		tcphy0_usb3: usb3-port {
58			#phy-cells = <0>;
59		};
60	};
61
62	tcphy1: phy@ff800000 {
63		compatible = "rockchip,rk3399-typec-phy";
64		reg = <0x0 0xff800000 0x0 0x40000>;
65		rockchip,grf = <&grf>;
66		extcon = <&fusb1>;
67		clocks = <&cru SCLK_UPHY1_TCPDCORE>,
68			 <&cru SCLK_UPHY1_TCPDPHY_REF>;
69		clock-names = "tcpdcore", "tcpdphy-ref";
70		assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
71		assigned-clock-rates = <50000000>;
72		resets = <&cru SRST_UPHY1>,
73			 <&cru SRST_UPHY1_PIPE_L00>,
74			 <&cru SRST_P_UPHY1_TCPHY>;
75		reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
76
77		tcphy1_dp: dp-port {
78			#phy-cells = <0>;
79		};
80
81		tcphy1_usb3: usb3-port {
82			#phy-cells = <0>;
83		};
84	};
85