1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: STMicroelectronics STM32 USB HS PHY controller binding 8 9description: 10 11 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI 12 switch. It controls PHY configuration and status, and the UTMI+ switch that 13 selects either OTG or HOST controller for the second PHY port. It also sets 14 PLL configuration. 15 16 USBPHYC 17 |_ PLL 18 | 19 |_ PHY port#1 _________________ HOST controller 20 | __ | 21 | / 1|________________| 22 |_ PHY port#2 ----| |________________ 23 | \_0| | 24 |_ UTMI switch_______| OTG controller 25 26maintainers: 27 - Amelie Delaunay <amelie.delaunay@foss.st.com> 28 29properties: 30 compatible: 31 const: st,stm32mp1-usbphyc 32 33 reg: 34 maxItems: 1 35 36 clocks: 37 maxItems: 1 38 39 resets: 40 maxItems: 1 41 42 "#address-cells": 43 const: 1 44 45 "#size-cells": 46 const: 0 47 48 vdda1v1-supply: 49 description: regulator providing 1V1 power supply to the PLL block 50 51 vdda1v8-supply: 52 description: regulator providing 1V8 power supply to the PLL block 53 54 '#clock-cells': 55 description: number of clock cells for ck_usbo_48m consumer 56 const: 0 57 58#Required child nodes: 59 60patternProperties: 61 "^usb-phy@[0|1]$": 62 type: object 63 description: 64 Each port the controller provides must be represented as a sub-node. 65 66 properties: 67 reg: 68 description: phy port index. 69 maxItems: 1 70 71 phy-supply: 72 description: regulator providing 3V3 power supply to the PHY. 73 74 "#phy-cells": 75 enum: [ 0x0, 0x1 ] 76 77 connector: 78 type: object 79 allOf: 80 - $ref: ../connector/usb-connector.yaml 81 properties: 82 vbus-supply: true 83 84 # It can be necessary to adjust the PHY settings to compensate parasitics, which can be due 85 # to USB connector/receptacle, routing, ESD protection component,... Here is the list of 86 # all optional parameters to tune the interface of the PHY (HS for High-Speed, FS for Full- 87 # Speed, LS for Low-Speed) 88 89 st,current-boost-microamp: 90 description: Current boosting in uA 91 enum: [ 1000, 2000 ] 92 93 st,no-lsfs-fb-cap: 94 description: Disables the LS/FS feedback capacitor 95 type: boolean 96 97 st,decrease-hs-slew-rate: 98 description: Decreases the HS driver slew rate by 10% 99 type: boolean 100 101 st,tune-hs-dc-level: 102 description: | 103 Tunes the HS driver DC level 104 - <0> normal level 105 - <1> increases the level by 5 to 7 mV 106 - <2> increases the level by 10 to 14 mV 107 - <3> decreases the level by 5 to 7 mV 108 $ref: /schemas/types.yaml#/definitions/uint32 109 minimum: 0 110 maximum: 3 111 default: 0 112 113 st,enable-fs-rftime-tuning: 114 description: Enables the FS rise/fall tuning option 115 type: boolean 116 117 st,enable-hs-rftime-reduction: 118 description: Enables the HS rise/fall reduction feature 119 type: boolean 120 121 st,trim-hs-current: 122 description: | 123 Controls HS driver current trimming for choke compensation 124 - <0> = 18.87 mA target current / nominal + 0% 125 - <1> = 19.165 mA target current / nominal + 1.56% 126 - <2> = 19.46 mA target current / nominal + 3.12% 127 - <3> = 19.755 mA target current / nominal + 4.68% 128 - <4> = 20.05 mA target current / nominal + 6.24% 129 - <5> = 20.345 mA target current / nominal + 7.8% 130 - <6> = 20.64 mA target current / nominal + 9.36% 131 - <7> = 20.935 mA target current / nominal + 10.92% 132 - <8> = 21.23 mA target current / nominal + 12.48% 133 - <9> = 21.525 mA target current / nominal + 14.04% 134 - <10> = 21.82 mA target current / nominal + 15.6% 135 - <11> = 22.115 mA target current / nominal + 17.16% 136 - <12> = 22.458 mA target current / nominal + 19.01% 137 - <13> = 22.755 mA target current / nominal + 20.58% 138 - <14> = 23.052 mA target current / nominal + 22.16% 139 - <15> = 23.348 mA target current / nominal + 23.73% 140 $ref: /schemas/types.yaml#/definitions/uint32 141 minimum: 0 142 maximum: 15 143 default: 0 144 145 st,trim-hs-impedance: 146 description: | 147 Controls HS driver impedance tuning for choke compensation 148 - <0> = no impedance offset 149 - <1> = reduce the impedance by 2 ohms 150 - <2> = reduce the impedance by 4 ohms 151 - <3> = reduce the impedance by 6 ohms 152 $ref: /schemas/types.yaml#/definitions/uint32 153 minimum: 0 154 maximum: 3 155 default: 0 156 157 st,tune-squelch-level: 158 description: | 159 Tunes the squelch DC threshold value 160 - <0> = no shift in threshold 161 - <1> = threshold shift by +7 mV 162 - <2> = threshold shift by -5 mV 163 - <3> = threshold shift by +14 mV 164 $ref: /schemas/types.yaml#/definitions/uint32 165 minimum: 0 166 maximum: 3 167 default: 0 168 169 st,enable-hs-rx-gain-eq: 170 description: Enables the HS Rx gain equalizer 171 type: boolean 172 173 st,tune-hs-rx-offset: 174 description: | 175 Adjusts the HS Rx offset 176 - <0> = no offset 177 - <1> = offset of +5 mV 178 - <2> = offset of +10 mV 179 - <3> = offset of -5 mV 180 $ref: /schemas/types.yaml#/definitions/uint32 181 minimum: 0 182 maximum: 3 183 default: 0 184 185 st,no-hs-ftime-ctrl: 186 description: Disables the HS fall time control of single ended signals during pre-emphasis 187 type: boolean 188 189 st,no-lsfs-sc: 190 description: Disables the short circuit protection in LS/FS driver 191 type: boolean 192 193 st,enable-hs-tx-staggering: 194 description: Enables the basic staggering in HS Tx mode 195 type: boolean 196 197 allOf: 198 - if: 199 properties: 200 reg: 201 const: 0 202 then: 203 properties: 204 "#phy-cells": 205 const: 0 206 else: 207 properties: 208 "#phy-cells": 209 const: 1 210 description: 211 The value is used to select UTMI switch output. 212 0 for OTG controller and 1 for Host controller. 213 214 required: 215 - reg 216 - phy-supply 217 - "#phy-cells" 218 219 additionalProperties: false 220 221required: 222 - compatible 223 - reg 224 - clocks 225 - "#address-cells" 226 - "#size-cells" 227 - vdda1v1-supply 228 - vdda1v8-supply 229 - usb-phy@0 230 - usb-phy@1 231 232additionalProperties: false 233 234examples: 235 - | 236 #include <dt-bindings/clock/stm32mp1-clks.h> 237 #include <dt-bindings/reset/stm32mp1-resets.h> 238 usbphyc: usbphyc@5a006000 { 239 compatible = "st,stm32mp1-usbphyc"; 240 reg = <0x5a006000 0x1000>; 241 clocks = <&rcc USBPHY_K>; 242 resets = <&rcc USBPHY_R>; 243 vdda1v1-supply = <®11>; 244 vdda1v8-supply = <®18>; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 #clock-cells = <0>; 248 249 usbphyc_port0: usb-phy@0 { 250 reg = <0>; 251 phy-supply = <&vdd_usb>; 252 #phy-cells = <0>; 253 st,tune-hs-dc-level = <2>; 254 st,enable-fs-rftime-tuning; 255 st,enable-hs-rftime-reduction; 256 st,trim-hs-current = <15>; 257 st,trim-hs-impedance = <1>; 258 st,tune-squelch-level = <3>; 259 st,tune-hs-rx-offset = <2>; 260 st,no-lsfs-sc; 261 connector { 262 compatible = "usb-a-connector"; 263 vbus-supply = <&vbus_sw>; 264 }; 265 }; 266 267 usbphyc_port1: usb-phy@1 { 268 reg = <1>; 269 phy-supply = <&vdd_usb>; 270 #phy-cells = <1>; 271 st,tune-hs-dc-level = <2>; 272 st,enable-fs-rftime-tuning; 273 st,enable-hs-rftime-reduction; 274 st,trim-hs-current = <15>; 275 st,trim-hs-impedance = <1>; 276 st,tune-squelch-level = <3>; 277 st,tune-hs-rx-offset = <2>; 278 st,no-lsfs-sc; 279 }; 280 }; 281... 282