1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Qualcomm QUSB2 phy controller
9
10maintainers:
11  - Manu Gautam <mgautam@codeaurora.org>
12
13description:
14  QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
15
16properties:
17  compatible:
18    oneOf:
19      - items:
20          - enum:
21              - qcom,ipq8074-qusb2-phy
22              - qcom,msm8996-qusb2-phy
23              - qcom,msm8998-qusb2-phy
24              - qcom,qcm2290-qusb2-phy
25              - qcom,sdm660-qusb2-phy
26              - qcom,ipq6018-qusb2-phy
27              - qcom,sm4250-qusb2-phy
28              - qcom,sm6115-qusb2-phy
29      - items:
30          - enum:
31              - qcom,sc7180-qusb2-phy
32              - qcom,sdm845-qusb2-phy
33          - const: qcom,qusb2-v2-phy
34  reg:
35    maxItems: 1
36
37  "#phy-cells":
38    const: 0
39
40  clocks:
41    minItems: 2
42    items:
43      - description: phy config clock
44      - description: 19.2 MHz ref clk
45      - description: phy interface clock (Optional)
46
47  clock-names:
48    minItems: 2
49    items:
50      - const: cfg_ahb
51      - const: ref
52      - const: iface
53
54  vdd-supply:
55    description:
56      Phandle to 0.9V regulator supply to PHY digital circuit.
57
58  vdda-pll-supply:
59    description:
60      Phandle to 1.8V regulator supply to PHY refclk pll block.
61
62  vdda-phy-dpdm-supply:
63    description:
64      Phandle to 3.1V regulator supply to Dp/Dm port signals.
65
66  resets:
67    maxItems: 1
68    description:
69      Phandle to reset to phy block.
70
71  nvmem-cells:
72    maxItems: 1
73    description:
74      Phandle to nvmem cell that contains 'HS Tx trim'
75      tuning parameter value for qusb2 phy.
76
77  qcom,tcsr-syscon:
78    description:
79      Phandle to TCSR syscon register region.
80    $ref: /schemas/types.yaml#/definitions/phandle
81
82if:
83  properties:
84    compatible:
85      contains:
86        const: qcom,qusb2-v2-phy
87then:
88  properties:
89    qcom,imp-res-offset-value:
90      description:
91        It is a 6 bit value that specifies offset to be
92        added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
93        tuning parameter that may vary for different boards of same SOC.
94      $ref: /schemas/types.yaml#/definitions/uint32
95      minimum: 0
96      maximum: 63
97      default: 0
98
99    qcom,bias-ctrl-value:
100      description:
101        It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
102        tuning parameter that may vary for different boards of same SOC.
103      $ref: /schemas/types.yaml#/definitions/uint32
104      minimum: 0
105      maximum: 63
106      default: 32
107
108    qcom,charge-ctrl-value:
109      description:
110        It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
111        tuning parameter that may vary for different boards of same SOC.
112      $ref: /schemas/types.yaml#/definitions/uint32
113      minimum: 0
114      maximum: 3
115      default: 0
116
117    qcom,hstx-trim-value:
118      description:
119        It is a 4 bit value that specifies tuning for HSTX
120        output current.
121        Possible range is - 15mA to 24mA (stepsize of 600 uA).
122        See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
123      $ref: /schemas/types.yaml#/definitions/uint32
124      minimum: 0
125      maximum: 15
126      default: 3
127
128    qcom,preemphasis-level:
129      description:
130        It is a 2 bit value that specifies pre-emphasis level.
131        Possible range is 0 to 15% (stepsize of 5%).
132        See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
133      $ref: /schemas/types.yaml#/definitions/uint32
134      minimum: 0
135      maximum: 3
136      default: 2
137
138    qcom,preemphasis-width:
139      description:
140        It is a 1 bit value that specifies how long the HSTX
141        pre-emphasis (specified using qcom,preemphasis-level) must be in
142        effect. Duration could be half-bit of full-bit.
143        See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
144      $ref: /schemas/types.yaml#/definitions/uint32
145      minimum: 0
146      maximum: 1
147      default: 0
148
149    qcom,hsdisc-trim-value:
150      description:
151        It is a 2 bit value tuning parameter that control disconnect
152        threshold and may vary for different boards of same SOC.
153      $ref: /schemas/types.yaml#/definitions/uint32
154      minimum: 0
155      maximum: 3
156      default: 0
157
158required:
159  - compatible
160  - reg
161  - "#phy-cells"
162  - clocks
163  - clock-names
164  - vdd-supply
165  - vdda-pll-supply
166  - vdda-phy-dpdm-supply
167  - resets
168
169additionalProperties: false
170
171examples:
172  - |
173    #include <dt-bindings/clock/qcom,gcc-msm8996.h>
174    hsusb_phy: phy@7411000 {
175        compatible = "qcom,msm8996-qusb2-phy";
176        reg = <0x7411000 0x180>;
177        #phy-cells = <0>;
178
179        clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
180                 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
181        clock-names = "cfg_ahb", "ref";
182
183        vdd-supply = <&pm8994_l28>;
184        vdda-pll-supply = <&pm8994_l12>;
185        vdda-phy-dpdm-supply = <&pm8994_l24>;
186
187        resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
188        nvmem-cells = <&qusb2p_hstx_trim>;
189    };
190