1Samsung GPIO and Pin Mux/Config controller 2 3Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware 4controller. It controls the input/output settings on the available pads/pins 5and also provides ability to multiplex and configure the output of various 6on-chip controllers onto these pads. 7 8Required Properties: 9- compatible: should be one of the following. 10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller, 11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller, 12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller, 13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller, 14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller, 15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller, 16 - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller. 17 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller. 18 - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller. 19 - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller. 20 - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller. 21 - "samsung,exynos5410-pinctrl": for Exynos5410 compatible pin-controller. 22 - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. 23 - "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller. 24 - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller. 25 - "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller. 26 - "samsung,exynosautov9-pinctrl": for ExynosAutov9 compatible pin-controller. 27 28- reg: Base address of the pin controller hardware module and length of 29 the address space it occupies. 30 31 - reg: Second base address of the pin controller if the specific registers 32 of the pin controller are separated into the different base address. 33 34 Eg: GPF[1-5] of Exynos5433 are separated into the two base address. 35 - First base address is for GPAx and GPF[1-5] external interrupt 36 registers. 37 - Second base address is for GPF[1-5] pinctrl registers. 38 39 pinctrl_0: pinctrl@10580000 { 40 compatible = "samsung,exynos5433-pinctrl"; 41 reg = <0x10580000 0x1a20>, <0x11090000 0x100>; 42 43 wakeup-interrupt-controller { 44 compatible = "samsung,exynos7-wakeup-eint"; 45 interrupts = <0 16 0>; 46 }; 47 }; 48 49- Pin banks as child nodes: Pin banks of the controller are represented by child 50 nodes of the controller node. Bank name is taken from name of the node. Each 51 bank node must contain following properties: 52 53 - gpio-controller: identifies the node as a gpio controller and pin bank. 54 - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO 55 binding is used, the amount of cells must be specified as 2. See the below 56 mentioned gpio binding representation for description of particular cells. 57 58 Eg: <&gpx2 6 0> 59 <[phandle of the gpio controller node] 60 [pin number within the gpio controller] 61 [flags]> 62 63 Values for gpio specifier: 64 - Pin number: is a value between 0 to 7. 65 - Flags: 0 - Active High 66 1 - Active Low 67 68- Pin mux/config groups as child nodes: The pin mux (selecting pin function 69 mode) and pin config (pull up/down, driver strength) settings are represented 70 as child nodes of the pin-controller node. There should be at least one 71 child node and there is no limit on the count of these child nodes. It is 72 also possible for a child node to consist of several further child nodes 73 to allow grouping multiple pinctrl groups into one. The format of second 74 level child nodes is exactly the same as for first level ones and is 75 described below. 76 77 The child node should contain a list of pin(s) on which a particular pin 78 function selection or pin configuration (or both) have to applied. This 79 list of pins is specified using the property name "samsung,pins". There 80 should be at least one pin specified for this property and there is no upper 81 limit on the count of pins that can be specified. The pins are specified 82 using pin names which are derived from the hardware manual of the SoC. As 83 an example, the pins in GPA0 bank of the pin controller can be represented 84 as "gpa0-0", "gpa0-1", "gpa0-2" and so on. The names should be in lower case. 85 The format of the pin names should be (as per the hardware manual) 86 "[pin bank name]-[pin number within the bank]". 87 88 The pin function selection that should be applied on the pins listed in the 89 child node is specified using the "samsung,pin-function" property. The value 90 of this property that should be applied to each of the pins listed in the 91 "samsung,pins" property should be picked from the hardware manual of the SoC 92 for the specified pin group. This property is optional in the child node if 93 no specific function selection is desired for the pins listed in the child 94 node. The value of this property is used as-is to program the pin-controller 95 function selector register of the pin-bank. 96 97 The child node can also optionally specify one or more of the pin 98 configuration that should be applied on all the pins listed in the 99 "samsung,pins" property of the child node. The following pin configuration 100 properties are supported. 101 102 - samsung,pin-val: Initial value of pin output buffer. 103 - samsung,pin-pud: Pull up/down configuration. 104 - samsung,pin-drv: Drive strength configuration. 105 - samsung,pin-pud-pdn: Pull up/down configuration in power down mode. 106 - samsung,pin-drv-pdn: Drive strength configuration in power down mode. 107 108 The values specified by these config properties should be derived from the 109 hardware manual and these values are programmed as-is into the pin 110 pull up/down and driver strength register of the pin-controller. 111 112 Note: A child should include at least a pin function selection property or 113 pin configuration property (one or more) or both. 114 115 The client nodes that require a particular pin function selection and/or 116 pin configuration should use the bindings listed in the "pinctrl-bindings.txt" 117 file. 118 119External GPIO and Wakeup Interrupts: 120 121The controller supports two types of external interrupts over gpio. The first 122is the external gpio interrupt and second is the external wakeup interrupts. 123The difference between the two is that the external wakeup interrupts can be 124used as system wakeup events. 125 126A. External GPIO Interrupts: For supporting external gpio interrupts, the 127 following properties should be specified in the pin-controller device node. 128 129 - interrupts: interrupt specifier for the controller. The format and value of 130 the interrupt specifier depends on the interrupt parent for the controller. 131 132 In addition, following properties must be present in node of every bank 133 of pins supporting GPIO interrupts: 134 135 - interrupt-controller: identifies the controller node as interrupt-parent. 136 - #interrupt-cells: the value of this property should be 2. 137 - First Cell: represents the external gpio interrupt number local to the 138 external gpio interrupt space of the controller. 139 - Second Cell: flags to identify the type of the interrupt 140 - 1 = rising edge triggered 141 - 2 = falling edge triggered 142 - 3 = rising and falling edge triggered 143 - 4 = high level triggered 144 - 8 = low level triggered 145 146B. External Wakeup Interrupts: For supporting external wakeup interrupts, a 147 child node representing the external wakeup interrupt controller should be 148 included in the pin-controller device node. 149 150 Only one pin-controller device node can include external wakeup interrupts 151 child node (in other words, only one External Wakeup Interrupts 152 pin-controller is supported). 153 154 This child node should include following properties: 155 156 - compatible: identifies the type of the external wakeup interrupt controller 157 The possible values are: 158 - samsung,s3c2410-wakeup-eint: represents wakeup interrupt controller 159 found on Samsung S3C24xx SoCs except S3C2412 and S3C2413, 160 - samsung,s3c2412-wakeup-eint: represents wakeup interrupt controller 161 found on Samsung S3C2412 and S3C2413 SoCs, 162 - samsung,s3c64xx-wakeup-eint: represents wakeup interrupt controller 163 found on Samsung S3C64xx SoCs, 164 - samsung,s5pv210-wakeup-eint: represents wakeup interrupt controller 165 found on Samsung S5Pv210 SoCs, 166 - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller 167 found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs. 168 - samsung,exynos7-wakeup-eint: represents wakeup interrupt controller 169 found on Samsung Exynos7 SoC. 170 - interrupts: interrupt used by multiplexed wakeup interrupts. 171 172 In addition, following properties must be present in node of every bank 173 of pins supporting wake-up interrupts: 174 175 - interrupt-controller: identifies the node as interrupt-parent. 176 - #interrupt-cells: the value of this property should be 2 177 - First Cell: represents the external wakeup interrupt number local to 178 the external wakeup interrupt space of the controller. 179 - Second Cell: flags to identify the type of the interrupt 180 - 1 = rising edge triggered 181 - 2 = falling edge triggered 182 - 3 = rising and falling edge triggered 183 - 4 = high level triggered 184 - 8 = low level triggered 185 186 Node of every bank of pins supporting direct wake-up interrupts (without 187 multiplexing) must contain following properties: 188 189 - interrupts: interrupts of the interrupt parent which are used for external 190 wakeup interrupts from pins of the bank, must contain interrupts for all 191 pins of the bank. 192 193Aliases: 194 195All the pin controller nodes should be represented in the aliases node using 196the following format 'pinctrl{n}' where n is a unique number for the alias. 197 198Aliases for controllers compatible with "samsung,exynos7-pinctrl": 199- pinctrl0: pin controller of ALIVE block, 200- pinctrl1: pin controller of BUS0 block, 201- pinctrl2: pin controller of NFC block, 202- pinctrl3: pin controller of TOUCH block, 203- pinctrl4: pin controller of FF block, 204- pinctrl5: pin controller of ESE block, 205- pinctrl6: pin controller of FSYS0 block, 206- pinctrl7: pin controller of FSYS1 block, 207- pinctrl8: pin controller of BUS1 block, 208- pinctrl9: pin controller of AUDIO block, 209 210Example: A pin-controller node with pin banks: 211 212 pinctrl_0: pinctrl@11400000 { 213 compatible = "samsung,exynos4210-pinctrl"; 214 reg = <0x11400000 0x1000>; 215 interrupts = <0 47 0>; 216 217 /* ... */ 218 219 /* Pin bank without external interrupts */ 220 gpy0: gpy0 { 221 gpio-controller; 222 #gpio-cells = <2>; 223 }; 224 225 /* ... */ 226 227 /* Pin bank with external GPIO or muxed wake-up interrupts */ 228 gpj0: gpj0 { 229 gpio-controller; 230 #gpio-cells = <2>; 231 232 interrupt-controller; 233 #interrupt-cells = <2>; 234 }; 235 236 /* ... */ 237 238 /* Pin bank with external direct wake-up interrupts */ 239 gpx0: gpx0 { 240 gpio-controller; 241 #gpio-cells = <2>; 242 243 interrupt-controller; 244 interrupt-parent = <&gic>; 245 interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, 246 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>; 247 #interrupt-cells = <2>; 248 }; 249 250 /* ... */ 251 }; 252 253Example 1: A pin-controller node with pin groups. 254 255 #include <dt-bindings/pinctrl/samsung.h> 256 257 pinctrl_0: pinctrl@11400000 { 258 compatible = "samsung,exynos4210-pinctrl"; 259 reg = <0x11400000 0x1000>; 260 interrupts = <0 47 0>; 261 262 /* ... */ 263 264 uart0_data: uart0-data { 265 samsung,pins = "gpa0-0", "gpa0-1"; 266 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 267 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 268 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 269 }; 270 271 uart0_fctl: uart0-fctl { 272 samsung,pins = "gpa0-2", "gpa0-3"; 273 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 274 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 275 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 276 }; 277 278 uart1_data: uart1-data { 279 samsung,pins = "gpa0-4", "gpa0-5"; 280 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 281 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 282 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 283 }; 284 285 uart1_fctl: uart1-fctl { 286 samsung,pins = "gpa0-6", "gpa0-7"; 287 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 288 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 289 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 290 }; 291 292 i2c2_bus: i2c2-bus { 293 samsung,pins = "gpa0-6", "gpa0-7"; 294 samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 295 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 296 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 297 }; 298 299 sd4_bus8: sd4-bus-width8 { 300 part-1 { 301 samsung,pins = "gpk0-3", "gpk0-4", 302 "gpk0-5", "gpk0-6"; 303 samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 304 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 305 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 306 }; 307 part-2 { 308 samsung,pins = "gpk1-3", "gpk1-4", 309 "gpk1-5", "gpk1-6"; 310 samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 311 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 312 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 313 }; 314 }; 315 }; 316 317Example 2: A pin-controller node with external wakeup interrupt controller node. 318 319 pinctrl_1: pinctrl@11000000 { 320 compatible = "samsung,exynos4210-pinctrl"; 321 reg = <0x11000000 0x1000>; 322 interrupts = <0 46 0> 323 324 /* ... */ 325 326 wakeup-interrupt-controller { 327 compatible = "samsung,exynos4210-wakeup-eint"; 328 interrupt-parent = <&gic>; 329 interrupts = <0 32 0>; 330 }; 331 }; 332 333Example 3: A uart client node that supports 'default' and 'flow-control' states. 334 335 uart@13800000 { 336 compatible = "samsung,exynos4210-uart"; 337 reg = <0x13800000 0x100>; 338 interrupts = <0 52 0>; 339 pinctrl-names = "default", "flow-control; 340 pinctrl-0 = <&uart0_data>; 341 pinctrl-1 = <&uart0_data>, <&uart0_fctl>; 342 }; 343 344Example 4: Set up the default pin state for uart controller. 345 346 static int s3c24xx_serial_probe(struct platform_device *pdev) { 347 struct pinctrl *pinctrl; 348 349 /* ... */ 350 351 pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 352 } 353 354Example 5: A display port client node that supports 'default' pinctrl state 355 and gpio binding. 356 357 display-port-controller { 358 /* ... */ 359 360 samsung,hpd-gpio = <&gpx2 6 0>; 361 pinctrl-names = "default"; 362 pinctrl-0 = <&dp_hpd>; 363 }; 364 365Example 6: Request the gpio for display port controller 366 367 static int exynos_dp_probe(struct platform_device *pdev) 368 { 369 int hpd_gpio, ret; 370 struct device *dev = &pdev->dev; 371 struct device_node *dp_node = dev->of_node; 372 373 /* ... */ 374 375 hpd_gpio = of_get_named_gpio(dp_node, "samsung,hpd-gpio", 0); 376 377 /* ... */ 378 379 ret = devm_gpio_request_one(&pdev->dev, hpd_gpio, GPIOF_IN, 380 "hpd_gpio"); 381 /* ... */ 382 } 383