1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright (C) 2020 SiFive, Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SiFive L2 Cache Controller
9
10maintainers:
11  - Sagar Kadam <sagar.kadam@sifive.com>
12  - Yash Shah <yash.shah@sifive.com>
13  - Paul Walmsley  <paul.walmsley@sifive.com>
14
15description:
16  The SiFive Level 2 Cache Controller is used to provide access to fast copies
17  of memory for masters in a Core Complex. The Level 2 Cache Controller also
18  acts as directory-based coherency manager.
19  All the properties in ePAPR/DeviceTree specification applies for this platform.
20
21allOf:
22  - $ref: /schemas/cache-controller.yaml#
23
24select:
25  properties:
26    compatible:
27      contains:
28        enum:
29          - sifive,fu540-c000-ccache
30          - sifive,fu740-c000-ccache
31
32  required:
33    - compatible
34
35properties:
36  compatible:
37    items:
38      - enum:
39          - sifive,fu540-c000-ccache
40          - sifive,fu740-c000-ccache
41      - const: cache
42
43  cache-block-size:
44    const: 64
45
46  cache-level:
47    const: 2
48
49  cache-sets:
50    const: 1024
51
52  cache-size:
53    const: 2097152
54
55  cache-unified: true
56
57  interrupts:
58    minItems: 3
59    items:
60      - description: DirError interrupt
61      - description: DataError interrupt
62      - description: DataFail interrupt
63      - description: DirFail interrupt
64
65  reg:
66    maxItems: 1
67
68  next-level-cache: true
69
70  memory-region:
71    maxItems: 1
72    description: |
73      The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
74      The reserved memory node should be defined as per the bindings in reserved-memory.txt.
75
76if:
77  properties:
78    compatible:
79      contains:
80        const: sifive,fu540-c000-ccache
81
82then:
83  properties:
84    interrupts:
85      description: |
86        Must contain entries for DirError, DataError and DataFail signals.
87      maxItems: 3
88
89else:
90  properties:
91    interrupts:
92      description: |
93        Must contain entries for DirError, DataError, DataFail, DirFail signals.
94      minItems: 4
95
96additionalProperties: false
97
98required:
99  - compatible
100  - cache-block-size
101  - cache-level
102  - cache-sets
103  - cache-size
104  - cache-unified
105  - interrupts
106  - reg
107
108examples:
109  - |
110    cache-controller@2010000 {
111        compatible = "sifive,fu540-c000-ccache", "cache";
112        cache-block-size = <64>;
113        cache-level = <2>;
114        cache-sets = <1024>;
115        cache-size = <2097152>;
116        cache-unified;
117        reg = <0x2010000 0x1000>;
118        interrupt-parent = <&plic0>;
119        interrupts = <1>,
120                     <2>,
121                     <3>;
122        next-level-cache = <&L25>;
123        memory-region = <&l2_lim>;
124    };
125