1* MediaTek Universal Asynchronous Receiver/Transmitter (UART)
2
3Required properties:
4- compatible should contain:
5  * "mediatek,mt2701-uart" for MT2701 compatible UARTS
6  * "mediatek,mt2712-uart" for MT2712 compatible UARTS
7  * "mediatek,mt6580-uart" for MT6580 compatible UARTS
8  * "mediatek,mt6582-uart" for MT6582 compatible UARTS
9  * "mediatek,mt6589-uart" for MT6589 compatible UARTS
10  * "mediatek,mt6755-uart" for MT6755 compatible UARTS
11  * "mediatek,mt6765-uart" for MT6765 compatible UARTS
12  * "mediatek,mt6779-uart" for MT6779 compatible UARTS
13  * "mediatek,mt6795-uart" for MT6795 compatible UARTS
14  * "mediatek,mt6797-uart" for MT6797 compatible UARTS
15  * "mediatek,mt7622-uart" for MT7622 compatible UARTS
16  * "mediatek,mt7623-uart" for MT7623 compatible UARTS
17  * "mediatek,mt7629-uart" for MT7629 compatible UARTS
18  * "mediatek,mt7986-uart", "mediatek,mt6577-uart" for MT7986 compatible UARTS
19  * "mediatek,mt8127-uart" for MT8127 compatible UARTS
20  * "mediatek,mt8135-uart" for MT8135 compatible UARTS
21  * "mediatek,mt8173-uart" for MT8173 compatible UARTS
22  * "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS
23  * "mediatek,mt8192-uart", "mediatek,mt6577-uart" for MT8192 compatible UARTS
24  * "mediatek,mt8195-uart", "mediatek,mt6577-uart" for MT8195 compatible UARTS
25  * "mediatek,mt8516-uart" for MT8516 compatible UARTS
26  * "mediatek,mt6577-uart" for MT6577 and all of the above
27
28- reg: The base address of the UART register bank.
29
30- interrupts:
31  index 0: an interrupt specifier for the UART controller itself
32  index 1: optional, an interrupt specifier with edge sensitivity on Rx pin to
33           support Rx in-band wake up. If one would like to use this feature,
34           one must create an addtional pinctrl to reconfigure Rx pin to normal
35           GPIO before suspend.
36
37- clocks : Must contain an entry for each entry in clock-names.
38  See ../clocks/clock-bindings.txt for details.
39- clock-names:
40  - "baud": The clock the baudrate is derived from
41  - "bus": The bus clock for register accesses (optional)
42
43For compatibility with older device trees an unnamed clock is used for the
44baud clock if the baudclk does not exist. Do not use this for new designs.
45
46Example:
47
48	uart0: serial@11006000 {
49		compatible = "mediatek,mt6589-uart", "mediatek,mt6577-uart";
50		reg = <0x11006000 0x400>;
51		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>,
52			     <GIC_SPI 52 IRQ_TYPE_EDGE_FALLING>;
53		clocks = <&uart_clk>, <&bus_clk>;
54		clock-names = "baud", "bus";
55		pinctrl-names = "default", "sleep";
56		pinctrl-0 = <&uart_pin>;
57		pinctrl-1 = <&uart_pin_sleep>;
58	};
59