1* Freescale QUICC Engine module (QE)
2This represents qe module that is installed on PowerQUICC II Pro.
3
4NOTE:  This is an interim binding; it should be updated to fit
5in with the CPM binding later in this document.
6
7Basically, it is a bus of devices, that could act more or less
8as a complete entity (UCC, USB etc ). All of them should be siblings on
9the "root" qe node, using the common properties from there.
10The description below applies to the qe of MPC8360 and
11more nodes and properties would be extended in the future.
12
13i) Root QE device
14
15Required properties:
16- compatible : should be "fsl,qe";
17- model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
18- reg : offset and length of the device registers.
19- bus-frequency : the clock frequency for QUICC Engine.
20- fsl,qe-num-riscs: define how many RISC engines the QE has.
21- fsl,qe-snums: This property has to be specified as '/bits/ 8' value,
22  defining the array of serial number (SNUM) values for the virtual
23  threads.
24
25Optional properties:
26- fsl,firmware-phandle:
27    Usage: required only if there is no fsl,qe-firmware child node
28    Value type: <phandle>
29    Definition: Points to a firmware node (see "QE Firmware Node" below)
30        that contains the firmware that should be uploaded for this QE.
31        The compatible property for the firmware node should say,
32        "fsl,qe-firmware".
33
34Recommended properties
35- brg-frequency : the internal clock source frequency for baud-rate
36  generators in Hz.
37
38Deprecated properties
39- fsl,qe-num-snums: define how many serial number(SNUM) the QE can use
40  for the threads. Use fsl,qe-snums instead to not only specify the
41  number of snums, but also their values.
42
43Example:
44     qe@e0100000 {
45	#address-cells = <1>;
46	#size-cells = <1>;
47	#interrupt-cells = <2>;
48	compatible = "fsl,qe";
49	ranges = <0 e0100000 00100000>;
50	reg = <e0100000 480>;
51	brg-frequency = <0>;
52	bus-frequency = <179A7B00>;
53	fsl,qe-snums = /bits/ 8 <
54		0x04 0x05 0x0C 0x0D 0x14 0x15 0x1C 0x1D
55		0x24 0x25 0x2C 0x2D 0x34 0x35 0x88 0x89
56		0x98 0x99 0xA8 0xA9 0xB8 0xB9 0xC8 0xC9
57		0xD8 0xD9 0xE8 0xE9>;
58     }
59
60* Multi-User RAM (MURAM)
61
62Required properties:
63- compatible : should be "fsl,qe-muram", "fsl,cpm-muram".
64- mode : the could be "host" or "slave".
65- ranges : Should be defined as specified in 1) to describe the
66   translation of MURAM addresses.
67- data-only : sub-node which defines the address area under MURAM
68   bus that can be allocated as data/parameter
69
70Example:
71
72     muram@10000 {
73	compatible = "fsl,qe-muram", "fsl,cpm-muram";
74	ranges = <0 00010000 0000c000>;
75
76	data-only@0{
77		compatible = "fsl,qe-muram-data",
78			     "fsl,cpm-muram-data";
79		reg = <0 c000>;
80	};
81     };
82
83* Interrupt Controller (IC)
84
85Required properties:
86- compatible : should be "fsl,qe-ic".
87- reg : Address range of IC register set.
88- interrupts : interrupts generated by the device.
89- interrupt-controller : this device is a interrupt controller.
90
91Example:
92
93	qeic: interrupt-controller@80 {
94		interrupt-controller;
95		compatible = "fsl,qe-ic";
96		#address-cells = <0>;
97		#interrupt-cells = <1>;
98		reg = <0x80 0x80>;
99		interrupts = <95 2 0 0  94 2 0 0>;
100	};
101
102* Serial Interface Block (SI)
103
104The SI manages the routing of eight TDM lines to the QE block serial drivers
105, the MCC and the UCCs, for receive and transmit.
106
107Required properties:
108- compatible : must be "fsl,<chip>-qe-si". For t1040, must contain
109  "fsl,t1040-qe-si".
110- reg : Address range of SI register set.
111
112Example:
113
114	si1: si@700 {
115		compatible = "fsl,t1040-qe-si";
116		reg = <0x700 0x80>;
117	};
118
119* Serial Interface Block RAM(SIRAM)
120
121store the routing entries of SI
122
123Required properties:
124- compatible : should be "fsl,<chip>-qe-siram". For t1040, must contain
125  "fsl,t1040-qe-siram".
126- reg : Address range of SI RAM.
127
128Example:
129
130	siram1: siram@1000 {
131		compatible = "fsl,t1040-qe-siram";
132		reg = <0x1000 0x800>;
133	};
134
135* QE Firmware Node
136
137This node defines a firmware binary that is embedded in the device tree, for
138the purpose of passing the firmware from bootloader to the kernel, or from
139the hypervisor to the guest.
140
141The firmware node itself contains the firmware binary contents, a compatible
142property, and any firmware-specific properties.  The node should be placed
143inside a QE node that needs it.  Doing so eliminates the need for a
144fsl,firmware-phandle property.  Other QE nodes that need the same firmware
145should define an fsl,firmware-phandle property that points to the firmware node
146in the first QE node.
147
148The fsl,firmware property can be specified in the DTS (possibly using incbin)
149or can be inserted by the boot loader at boot time.
150
151Required properties:
152  - compatible
153      Usage: required
154      Value type: <string>
155      Definition: A standard property.  Specify a string that indicates what
156          kind of firmware it is.  For QE, this should be "fsl,qe-firmware".
157
158   - fsl,firmware
159      Usage: required
160      Value type: <prop-encoded-array>, encoded as an array of bytes
161      Definition: A standard property.  This property contains the firmware
162          binary "blob".
163
164Example:
165	qe1@e0080000 {
166		compatible = "fsl,qe";
167		qe_firmware:qe-firmware {
168			compatible = "fsl,qe-firmware";
169			fsl,firmware = [0x70 0xcd 0x00 0x00 0x01 0x46 0x45 ...];
170		};
171		...
172	};
173
174	qe2@e0090000 {
175		compatible = "fsl,qe";
176		fsl,firmware-phandle = <&qe_firmware>;
177		...
178	};
179