1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Cadence Quad SPI controller
8
9maintainers:
10  - Pratyush Yadav <p.yadav@ti.com>
11
12allOf:
13  - $ref: spi-controller.yaml#
14  - if:
15      properties:
16        compatible:
17          contains:
18            const: xlnx,versal-ospi-1.0
19    then:
20      required:
21        - power-domains
22
23properties:
24  compatible:
25    oneOf:
26      - items:
27          - enum:
28              - ti,k2g-qspi
29              - ti,am654-ospi
30              - intel,lgm-qspi
31              - xlnx,versal-ospi-1.0
32              - intel,socfpga-qspi
33          - const: cdns,qspi-nor
34      - const: cdns,qspi-nor
35
36  reg:
37    items:
38      - description: the controller register set
39      - description: the controller data area
40
41  interrupts:
42    maxItems: 1
43
44  clocks:
45    maxItems: 1
46
47  cdns,fifo-depth:
48    description:
49      Size of the data FIFO in words.
50    $ref: "/schemas/types.yaml#/definitions/uint32"
51    enum: [ 128, 256 ]
52    default: 128
53
54  cdns,fifo-width:
55    $ref: /schemas/types.yaml#/definitions/uint32
56    description:
57      Bus width of the data FIFO in bytes.
58    default: 4
59
60  cdns,trigger-address:
61    $ref: /schemas/types.yaml#/definitions/uint32
62    description:
63      32-bit indirect AHB trigger address.
64
65  cdns,is-decoded-cs:
66    type: boolean
67    description:
68      Flag to indicate whether decoder is used to select different chip select
69      for different memory regions.
70
71  cdns,rclk-en:
72    type: boolean
73    description:
74      Flag to indicate that QSPI return clock is used to latch the read
75      data rather than the QSPI clock. Make sure that QSPI return clock
76      is populated on the board before using this property.
77
78  power-domains:
79    maxItems: 1
80
81  resets:
82    maxItems: 2
83
84  reset-names:
85    minItems: 1
86    maxItems: 2
87    items:
88      enum: [ qspi, qspi-ocp ]
89
90# subnode's properties
91patternProperties:
92  "@[0-9a-f]+$":
93    type: object
94    description:
95      Flash device uses the below defined properties in the subnode.
96
97    properties:
98      cdns,read-delay:
99        $ref: /schemas/types.yaml#/definitions/uint32
100        description:
101          Delay for read capture logic, in clock cycles.
102
103      cdns,tshsl-ns:
104        description:
105          Delay in nanoseconds for the length that the master mode chip select
106          outputs are de-asserted between transactions.
107
108      cdns,tsd2d-ns:
109        description:
110          Delay in nanoseconds between one chip select being de-activated
111          and the activation of another.
112
113      cdns,tchsh-ns:
114        description:
115          Delay in nanoseconds between last bit of current transaction and
116          deasserting the device chip select (qspi_n_ss_out).
117
118      cdns,tslch-ns:
119        description:
120          Delay in nanoseconds between setting qspi_n_ss_out low and
121          first bit transfer.
122
123required:
124  - compatible
125  - reg
126  - interrupts
127  - clocks
128  - cdns,fifo-depth
129  - cdns,fifo-width
130  - cdns,trigger-address
131  - '#address-cells'
132  - '#size-cells'
133
134unevaluatedProperties: false
135
136examples:
137  - |
138    qspi: spi@ff705000 {
139      compatible = "cdns,qspi-nor";
140      #address-cells = <1>;
141      #size-cells = <0>;
142      reg = <0xff705000 0x1000>,
143            <0xffa00000 0x1000>;
144      interrupts = <0 151 4>;
145      clocks = <&qspi_clk>;
146      cdns,fifo-depth = <128>;
147      cdns,fifo-width = <4>;
148      cdns,trigger-address = <0x00000000>;
149      resets = <&rst 0x1>, <&rst 0x2>;
150      reset-names = "qspi", "qspi-ocp";
151
152      flash@0 {
153              compatible = "jedec,spi-nor";
154              reg = <0x0>;
155      };
156    };
157