1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sram/sram.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Generic on-chip SRAM
8
9maintainers:
10  - Rob Herring <robh@kernel.org>
11
12description: |+
13  Simple IO memory regions to be managed by the genalloc API.
14
15  Each child of the sram node specifies a region of reserved memory. Each
16  child node should use a 'reg' property to specify a specific range of
17  reserved memory.
18
19  Following the generic-names recommended practice, node names should
20  reflect the purpose of the node. Unit address (@<address>) should be
21  appended to the name.
22
23properties:
24  $nodename:
25    pattern: "^sram(@.*)?"
26
27  compatible:
28    contains:
29      enum:
30        - mmio-sram
31        - amlogic,meson-gxbb-sram
32        - arm,juno-sram-ns
33        - atmel,sama5d2-securam
34        - qcom,rpm-msg-ram
35        - rockchip,rk3288-pmu-sram
36
37  reg:
38    maxItems: 1
39
40  clocks:
41    maxItems: 1
42    description:
43      A list of phandle and clock specifier pair that controls the single
44      SRAM clock.
45
46  "#address-cells":
47    const: 1
48
49  "#size-cells":
50    const: 1
51
52  ranges:
53    maxItems: 1
54    description:
55      Should translate from local addresses within the sram to bus addresses.
56
57  no-memory-wc:
58    description:
59      The flag indicating, that SRAM memory region has not to be remapped
60      as write combining. WC is used by default.
61    type: boolean
62
63patternProperties:
64  "^([a-z0-9]*-)?sram(-section)?@[a-f0-9]+$":
65    type: object
66    description:
67      Each child of the sram node specifies a region of reserved memory.
68    properties:
69      compatible:
70        description:
71          Should contain a vendor specific string in the form
72          <vendor>,[<device>-]<usage>
73        contains:
74          enum:
75            - allwinner,sun4i-a10-sram-a3-a4
76            - allwinner,sun4i-a10-sram-c1
77            - allwinner,sun4i-a10-sram-d
78            - allwinner,sun9i-a80-smp-sram
79            - allwinner,sun50i-a64-sram-c
80            - amlogic,meson8-ao-arc-sram
81            - amlogic,meson8b-ao-arc-sram
82            - amlogic,meson8-smp-sram
83            - amlogic,meson8b-smp-sram
84            - amlogic,meson-gxbb-scp-shmem
85            - amlogic,meson-axg-scp-shmem
86            - arm,juno-scp-shmem
87            - arm,scmi-shmem
88            - arm,scp-shmem
89            - renesas,smp-sram
90            - rockchip,rk3066-smp-sram
91            - samsung,exynos4210-sysram
92            - samsung,exynos4210-sysram-ns
93            - socionext,milbeaut-smp-sram
94
95      reg:
96        description:
97          IO mem address range, relative to the SRAM range.
98        maxItems: 1
99
100      pool:
101        description:
102          Indicates that the particular reserved SRAM area is addressable
103          and in use by another device or devices.
104        type: boolean
105
106      export:
107        description:
108          Indicates that the reserved SRAM area may be accessed outside
109          of the kernel, e.g. by bootloader or userspace.
110        type: boolean
111
112      protect-exec:
113        description: |
114          Same as 'pool' above but with the additional constraint that code
115          will be run from the region and that the memory is maintained as
116          read-only, executable during code execution. NOTE: This region must
117          be page aligned on start and end in order to properly allow
118          manipulation of the page attributes.
119        type: boolean
120
121      label:
122        description:
123          The name for the reserved partition, if omitted, the label is taken
124          from the node name excluding the unit address.
125
126    required:
127      - reg
128
129    additionalProperties: false
130
131required:
132  - compatible
133  - reg
134
135if:
136  properties:
137    compatible:
138      contains:
139        enum:
140          - qcom,rpm-msg-ram
141          - rockchip,rk3288-pmu-sram
142
143else:
144  required:
145    - "#address-cells"
146    - "#size-cells"
147    - ranges
148
149additionalProperties: false
150
151examples:
152  - |
153    sram@5c000000 {
154        compatible = "mmio-sram";
155        reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
156
157        #address-cells = <1>;
158        #size-cells = <1>;
159        ranges = <0 0x5c000000 0x40000>;
160
161        smp-sram@100 {
162            reg = <0x100 0x50>;
163        };
164
165        device-sram@1000 {
166            reg = <0x1000 0x1000>;
167            pool;
168        };
169
170        exported-sram@20000 {
171            reg = <0x20000 0x20000>;
172            export;
173        };
174    };
175
176  - |
177    // Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
178    // of the secondary cores. Once the core gets powered up it executes the
179    // code that is residing at some specific location of the SYSRAM.
180    //
181    // Therefore reserved section sub-nodes have to be added to the mmio-sram
182    // declaration. These nodes are of two types depending upon secure or
183    // non-secure execution environment.
184    sram@2020000 {
185        compatible = "mmio-sram";
186        reg = <0x02020000 0x54000>;
187        #address-cells = <1>;
188        #size-cells = <1>;
189        ranges = <0 0x02020000 0x54000>;
190
191        smp-sram@0 {
192            compatible = "samsung,exynos4210-sysram";
193            reg = <0x0 0x1000>;
194        };
195
196        smp-sram@53000 {
197            compatible = "samsung,exynos4210-sysram-ns";
198            reg = <0x53000 0x1000>;
199        };
200    };
201
202  - |
203    // Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
204    // Once the core gets powered up it executes the code that is residing at a
205    // specific location.
206    //
207    // Therefore a reserved section sub-node has to be added to the mmio-sram
208    // declaration.
209    sram@d9000000 {
210        compatible = "mmio-sram";
211        reg = <0xd9000000 0x20000>;
212        #address-cells = <1>;
213        #size-cells = <1>;
214        ranges = <0 0xd9000000 0x20000>;
215
216        smp-sram@1ff80 {
217            compatible = "amlogic,meson8b-smp-sram";
218            reg = <0x1ff80 0x8>;
219        };
220    };
221
222  - |
223    sram@e63c0000 {
224        compatible = "mmio-sram";
225        reg = <0xe63c0000 0x1000>;
226        #address-cells = <1>;
227        #size-cells = <1>;
228        ranges = <0 0xe63c0000 0x1000>;
229
230        smp-sram@0 {
231            compatible = "renesas,smp-sram";
232            reg = <0 0x10>;
233        };
234    };
235
236  - |
237    sram@10080000 {
238        compatible = "mmio-sram";
239        reg = <0x10080000 0x10000>;
240        #address-cells = <1>;
241        #size-cells = <1>;
242        ranges;
243
244        smp-sram@10080000 {
245            compatible = "rockchip,rk3066-smp-sram";
246            reg = <0x10080000 0x50>;
247        };
248    };
249
250  - |
251    // Rockchip's rk3288 SoC uses the sram of pmu to store the function of
252    // resume from maskrom(the 1st level loader). This is a common use of
253    // the "pmu-sram" because it keeps power even in low power states
254    // in the system.
255    sram@ff720000 {
256      compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
257      reg = <0xff720000 0x1000>;
258    };
259
260  - |
261    // Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
262    // primary core (cpu0). Once the core gets powered up it checks if a magic
263    // value is set at a specific location. If it is then the BROM will jump
264    // to the software entry address, instead of executing a standard boot.
265    //
266    // Also there are no "secure-only" properties. The implementation should
267    // check if this SRAM is usable first.
268    sram@20000 {
269        // 256 KiB secure SRAM at 0x20000
270        compatible = "mmio-sram";
271        reg = <0x00020000 0x40000>;
272        #address-cells = <1>;
273        #size-cells = <1>;
274        ranges = <0 0x00020000 0x40000>;
275
276        smp-sram@1000 {
277            // This is checked by BROM to determine if
278            // cpu0 should jump to SMP entry vector
279            compatible = "allwinner,sun9i-a80-smp-sram";
280            reg = <0x1000 0x8>;
281        };
282    };
283
284  - |
285    sram@0 {
286        compatible = "mmio-sram";
287        reg = <0x0 0x10000>;
288        #address-cells = <1>;
289        #size-cells = <1>;
290        ranges = <0 0x0 0x10000>;
291
292        smp-sram@f100 {
293            compatible = "socionext,milbeaut-smp-sram";
294            reg = <0xf100 0x20>;
295        };
296    };
297