1* USB2 ChipIdea USB controller for ci13xxx
2
3Required properties:
4- compatible: should be one of:
5	"fsl,imx23-usb"
6	"fsl,imx27-usb"
7	"fsl,imx28-usb"
8	"fsl,imx6q-usb"
9	"fsl,imx6sl-usb"
10	"fsl,imx6sx-usb"
11	"fsl,imx6ul-usb"
12	"fsl,imx7d-usb"
13	"fsl,imx7ulp-usb"
14	"lsi,zevio-usb"
15	"qcom,ci-hdrc"
16	"chipidea,usb2"
17	"xlnx,zynq-usb-2.20a"
18	"nvidia,tegra20-udc"
19	"nvidia,tegra30-udc"
20	"nvidia,tegra114-udc"
21	"nvidia,tegra124-udc"
22- reg: base address and length of the registers
23- interrupts: interrupt for the USB controller
24
25Recommended properies:
26- phy_type: the type of the phy connected to the core. Should be one
27  of "utmi", "utmi_wide", "ulpi", "serial" or "hsic". Without this
28  property the PORTSC register won't be touched.
29- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
30
31Deprecated properties:
32- usb-phy:      phandle for the PHY device. Use "phys" instead.
33- fsl,usbphy: phandle of usb phy that connects to the port. Use "phys" instead.
34
35Optional properties:
36- clocks: reference to the USB clock
37- phys: reference to the USB PHY
38- phy-names: should be "usb-phy"
39- vbus-supply: reference to the VBUS regulator
40- maximum-speed: limit the maximum connection speed to "full-speed".
41- tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts
42- itc-setting: interrupt threshold control register control, the setting
43  should be aligned with ITC bits at register USBCMD.
44- ahb-burst-config: it is vendor dependent, the required value should be
45  aligned with AHBBRST at SBUSCFG, the range is from 0x0 to 0x7. This
46  property is used to change AHB burst configuration, check the chipidea
47  spec for meaning of each value. If this property is not existed, it
48  will use the reset value.
49- tx-burst-size-dword: it is vendor dependent, the tx burst size in dword
50  (4 bytes), This register represents the maximum length of a the burst
51  in 32-bit words while moving data from system memory to the USB
52  bus, the value of this property will only take effect if property
53  "ahb-burst-config" is set to 0, if this property is missing the reset
54  default of the hardware implementation will be used.
55- rx-burst-size-dword: it is vendor dependent, the rx burst size in dword
56  (4 bytes), This register represents the maximum length of a the burst
57  in 32-bit words while moving data from the USB bus to system memory,
58  the value of this property will only take effect if property
59  "ahb-burst-config" is set to 0, if this property is missing the reset
60  default of the hardware implementation will be used.
61- extcon: phandles to external connector devices. First phandle should point to
62  external connector, which provide "USB" cable events, the second should point
63  to external connector device, which provide "USB-HOST" cable events. If one
64  of the external connector devices is not required, empty <0> phandle should
65  be specified.
66- phy-clkgate-delay-us: the delay time (us) between putting the PHY into
67  low power mode and gating the PHY clock.
68- non-zero-ttctrl-ttha: after setting this property, the value of register
69  ttctrl.ttha will be 0x7f; if not, the value will be 0x0, this is the default
70  value. It needs to be very carefully for setting this property, it is
71  recommended that consult with your IC engineer before setting this value.
72  On the most of chipidea platforms, the "usage_tt" flag at RTL is 0, so this
73  property only affects siTD.
74  If this property is not set, the max packet size is 1023 bytes, and if
75  the total of packet size for pervious transactions are more than 256 bytes,
76  it can't accept any transactions within this frame. The use case is single
77  transaction, but higher frame rate.
78  If this property is set, the max packet size is 188 bytes, it can handle
79  more transactions than above case, it can accept transactions until it
80  considers the left room size within frame is less than 188 bytes, software
81  needs to make sure it does not send more than 90%
82  maximum_periodic_data_per_frame. The use case is multiple transactions, but
83  less frame rate.
84- mux-controls: The mux control for toggling host/device output of this
85  controller. It's expected that a mux state of 0 indicates device mode and a
86  mux state of 1 indicates host mode.
87- mux-control-names: Shall be "usb_switch" if mux-controls is specified.
88- pinctrl-names: Names for optional pin modes in "default", "host", "device".
89  In case of HSIC-mode, "idle" and "active" pin modes are mandatory. In this
90  case, the "idle" state needs to pull down the data and strobe pin
91  and the "active" state needs to pull up the strobe pin.
92- pinctrl-n: alternate pin modes
93
94i.mx specific properties
95- fsl,usbmisc: phandler of non-core register device, with one
96  argument that indicate usb controller index
97- disable-over-current: disable over current detect
98- over-current-active-low: over current signal polarity is active low.
99- over-current-active-high: over current signal polarity is active high.
100  It's recommended to specify the over current polarity.
101- power-active-high: power signal polarity is active high
102- external-vbus-divider: enables off-chip resistor divider for Vbus
103- samsung,picophy-pre-emp-curr-control: HS Transmitter Pre-Emphasis Current
104  Control. This signal controls the amount of current sourced to the
105  USB_OTG*_DP and USB_OTG*_DN pins after a J-to-K or K-to-J transition.
106  The range is from 0x0 to 0x3, the default value is 0x1.
107  Details can refer to TXPREEMPAMPTUNE0 bits of USBNC_n_PHY_CFG1.
108- samsung,picophy-dc-vol-level-adjust: HS DC Voltage Level Adjustment.
109  Adjust the high-speed transmitter DC level voltage.
110  The range is from 0x0 to 0xf, the default value is 0x3.
111  Details can refer to TXVREFTUNE0 bits of USBNC_n_PHY_CFG1.
112
113Example:
114
115	usb@f7ed0000 {
116		compatible = "chipidea,usb2";
117		reg = <0xf7ed0000 0x10000>;
118		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
119		clocks = <&chip CLKID_USB0>;
120		phys = <&usb_phy0>;
121		phy-names = "usb-phy";
122		vbus-supply = <&reg_usb0_vbus>;
123		itc-setting = <0x4>; /* 4 micro-frames */
124		 /* Incremental burst of unspecified length */
125		ahb-burst-config = <0x0>;
126		tx-burst-size-dword = <0x10>; /* 64 bytes */
127		rx-burst-size-dword = <0x10>;
128		extcon = <0>, <&usb_id>;
129		phy-clkgate-delay-us = <400>;
130		mux-controls = <&usb_switch>;
131		mux-control-names = "usb_switch";
132	};
133
134Example for HSIC:
135
136	usb@2184400 {
137		compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
138		reg = <0x02184400 0x200>;
139		interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
140		clocks = <&clks IMX6QDL_CLK_USBOH3>;
141		fsl,usbphy = <&usbphynop1>;
142		fsl,usbmisc = <&usbmisc 2>;
143		phy_type = "hsic";
144		dr_mode = "host";
145		ahb-burst-config = <0x0>;
146		tx-burst-size-dword = <0x10>;
147		rx-burst-size-dword = <0x10>;
148		pinctrl-names = "idle", "active";
149		pinctrl-0 = <&pinctrl_usbh2_idle>;
150		pinctrl-1 = <&pinctrl_usbh2_active>;
151		#address-cells = <1>;
152		#size-cells = <0>;
153
154		usbnet: smsc@1 {
155			compatible = "usb424,9730";
156			reg = <1>;
157		};
158	};
159