1================================
2Register Usage for Linux/PA-RISC
3================================
4
5[ an asterisk is used for planned usage which is currently unimplemented ]
6
7General Registers as specified by ABI
8=====================================
9
10Control Registers
11-----------------
12
13===============================	===============================================
14CR 0 (Recovery Counter)		used for ptrace
15CR 1-CR 7(undefined)		unused
16CR 8 (Protection ID)		per-process value*
17CR 9, 12, 13 (PIDS)		unused
18CR10 (CCR)			lazy FPU saving*
19CR11				as specified by ABI (SAR)
20CR14 (interruption vector)	initialized to fault_vector
21CR15 (EIEM)			initialized to all ones*
22CR16 (Interval Timer)		read for cycle count/write starts Interval Tmr
23CR17-CR22			interruption parameters
24CR19				Interrupt Instruction Register
25CR20				Interrupt Space Register
26CR21				Interrupt Offset Register
27CR22				Interrupt PSW
28CR23 (EIRR)			read for pending interrupts/write clears bits
29CR24 (TR 0)			Kernel Space Page Directory Pointer
30CR25 (TR 1)			User   Space Page Directory Pointer
31CR26 (TR 2)			not used
32CR27 (TR 3)			Thread descriptor pointer
33CR28 (TR 4)			not used
34CR29 (TR 5)			not used
35CR30 (TR 6)			current / 0
36CR31 (TR 7)			Temporary register, used in various places
37===============================	===============================================
38
39Space Registers (kernel mode)
40-----------------------------
41
42===============================	===============================================
43SR0				temporary space register
44SR4-SR7 			set to 0
45SR1				temporary space register
46SR2				kernel should not clobber this
47SR3				used for userspace accesses (current process)
48===============================	===============================================
49
50Space Registers (user mode)
51---------------------------
52
53===============================	===============================================
54SR0				temporary space register
55SR1                             temporary space register
56SR2                             holds space of linux gateway page
57SR3                             holds user address space value while in kernel
58SR4-SR7                         Defines short address space for user/kernel
59===============================	===============================================
60
61
62Processor Status Word
63---------------------
64
65===============================	===============================================
66W (64-bit addresses)		0
67E (Little-endian)		0
68S (Secure Interval Timer)	0
69T (Taken Branch Trap)		0
70H (Higher-privilege trap)	0
71L (Lower-privilege trap)	0
72N (Nullify next instruction)	used by C code
73X (Data memory break disable)	0
74B (Taken Branch)		used by C code
75C (code address translation)	1, 0 while executing real-mode code
76V (divide step correction)	used by C code
77M (HPMC mask)			0, 1 while executing HPMC handler*
78C/B (carry/borrow bits)		used by C code
79O (ordered references)		1*
80F (performance monitor)		0
81R (Recovery Counter trap)	0
82Q (collect interruption state)	1 (0 in code directly preceding an rfi)
83P (Protection Identifiers)	1*
84D (Data address translation)	1, 0 while executing real-mode code
85I (external interrupt mask)	used by cli()/sti() macros
86===============================	===============================================
87
88"Invisible" Registers
89---------------------
90
91===============================	===============================================
92PSW default W value		0
93PSW default E value		0
94Shadow Registers		used by interruption handler code
95TOC enable bit			1
96===============================	===============================================
97
98-------------------------------------------------------------------------
99
100The PA-RISC architecture defines 7 registers as "shadow registers".
101Those are used in RETURN FROM INTERRUPTION AND RESTORE instruction to reduce
102the state save and restore time by eliminating the need for general register
103(GR) saves and restores in interruption handlers.
104Shadow registers are the GRs 1, 8, 9, 16, 17, 24, and 25.
105
106-------------------------------------------------------------------------
107
108Register usage notes, originally from John Marvin, with some additional
109notes from Randolph Chung.
110
111For the general registers:
112
113r1,r2,r19-r26,r28,r29 & r31 can be used without saving them first. And of
114course, you need to save them if you care about them, before calling
115another procedure. Some of the above registers do have special meanings
116that you should be aware of:
117
118    r1:
119	The addil instruction is hardwired to place its result in r1,
120	so if you use that instruction be aware of that.
121
122    r2:
123	This is the return pointer. In general you don't want to
124	use this, since you need the pointer to get back to your
125	caller. However, it is grouped with this set of registers
126	since the caller can't rely on the value being the same
127	when you return, i.e. you can copy r2 to another register
128	and return through that register after trashing r2, and
129	that should not cause a problem for the calling routine.
130
131    r19-r22:
132	these are generally regarded as temporary registers.
133	Note that in 64 bit they are arg7-arg4.
134
135    r23-r26:
136	these are arg3-arg0, i.e. you can use them if you
137	don't care about the values that were passed in anymore.
138
139    r28,r29:
140	are ret0 and ret1. They are what you pass return values
141	in. r28 is the primary return. When returning small structures
142	r29 may also be used to pass data back to the caller.
143
144    r30:
145	stack pointer
146
147    r31:
148	the ble instruction puts the return pointer in here.
149
150
151    r3-r18,r27,r30 need to be saved and restored. r3-r18 are just
152    general purpose registers. r27 is the data pointer, and is
153    used to make references to global variables easier. r30 is
154    the stack pointer.
155