1// SPDX-License-Identifier: GPL-2.0 2#include "bcm283x.dtsi" 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/soc/bcm2835-pm.h> 6 7/ { 8 compatible = "brcm,bcm2711"; 9 10 #address-cells = <2>; 11 #size-cells = <1>; 12 13 interrupt-parent = <&gicv2>; 14 15 vc4: gpu { 16 compatible = "brcm,bcm2711-vc5"; 17 status = "disabled"; 18 }; 19 20 clk_27MHz: clk-27M { 21 #clock-cells = <0>; 22 compatible = "fixed-clock"; 23 clock-frequency = <27000000>; 24 clock-output-names = "27MHz-clock"; 25 }; 26 27 clk_108MHz: clk-108M { 28 #clock-cells = <0>; 29 compatible = "fixed-clock"; 30 clock-frequency = <108000000>; 31 clock-output-names = "108MHz-clock"; 32 }; 33 34 soc { 35 /* 36 * Defined ranges: 37 * Common BCM283x peripherals 38 * BCM2711-specific peripherals 39 * ARM-local peripherals 40 */ 41 ranges = <0x7e000000 0x0 0xfe000000 0x01800000>, 42 <0x7c000000 0x0 0xfc000000 0x02000000>, 43 <0x40000000 0x0 0xff800000 0x00800000>; 44 /* Emulate a contiguous 30-bit address range for DMA */ 45 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>; 46 47 /* 48 * This node is the provider for the enable-method for 49 * bringing up secondary cores. 50 */ 51 local_intc: local_intc@40000000 { 52 compatible = "brcm,bcm2836-l1-intc"; 53 reg = <0x40000000 0x100>; 54 }; 55 56 gicv2: interrupt-controller@40041000 { 57 interrupt-controller; 58 #interrupt-cells = <3>; 59 compatible = "arm,gic-400"; 60 reg = <0x40041000 0x1000>, 61 <0x40042000 0x2000>, 62 <0x40044000 0x2000>, 63 <0x40046000 0x2000>; 64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 65 IRQ_TYPE_LEVEL_HIGH)>; 66 }; 67 68 avs_monitor: avs-monitor@7d5d2000 { 69 compatible = "brcm,bcm2711-avs-monitor", 70 "syscon", "simple-mfd"; 71 reg = <0x7d5d2000 0xf00>; 72 73 thermal: thermal { 74 compatible = "brcm,bcm2711-thermal"; 75 #thermal-sensor-cells = <0>; 76 }; 77 }; 78 79 dma: dma@7e007000 { 80 compatible = "brcm,bcm2835-dma"; 81 reg = <0x7e007000 0xb00>; 82 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 89 /* DMA lite 7 - 10 */ 90 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 94 interrupt-names = "dma0", 95 "dma1", 96 "dma2", 97 "dma3", 98 "dma4", 99 "dma5", 100 "dma6", 101 "dma7", 102 "dma8", 103 "dma9", 104 "dma10"; 105 #dma-cells = <1>; 106 brcm,dma-channel-mask = <0x07f5>; 107 }; 108 109 pm: watchdog@7e100000 { 110 compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; 111 #power-domain-cells = <1>; 112 #reset-cells = <1>; 113 reg = <0x7e100000 0x114>, 114 <0x7e00a000 0x24>, 115 <0x7ec11000 0x20>; 116 clocks = <&clocks BCM2835_CLOCK_V3D>, 117 <&clocks BCM2835_CLOCK_PERI_IMAGE>, 118 <&clocks BCM2835_CLOCK_H264>, 119 <&clocks BCM2835_CLOCK_ISP>; 120 clock-names = "v3d", "peri_image", "h264", "isp"; 121 system-power-controller; 122 }; 123 124 rng@7e104000 { 125 compatible = "brcm,bcm2711-rng200"; 126 reg = <0x7e104000 0x28>; 127 }; 128 129 uart2: serial@7e201400 { 130 compatible = "arm,pl011", "arm,primecell"; 131 reg = <0x7e201400 0x200>; 132 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 133 clocks = <&clocks BCM2835_CLOCK_UART>, 134 <&clocks BCM2835_CLOCK_VPU>; 135 clock-names = "uartclk", "apb_pclk"; 136 arm,primecell-periphid = <0x00241011>; 137 status = "disabled"; 138 }; 139 140 uart3: serial@7e201600 { 141 compatible = "arm,pl011", "arm,primecell"; 142 reg = <0x7e201600 0x200>; 143 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 144 clocks = <&clocks BCM2835_CLOCK_UART>, 145 <&clocks BCM2835_CLOCK_VPU>; 146 clock-names = "uartclk", "apb_pclk"; 147 arm,primecell-periphid = <0x00241011>; 148 status = "disabled"; 149 }; 150 151 uart4: serial@7e201800 { 152 compatible = "arm,pl011", "arm,primecell"; 153 reg = <0x7e201800 0x200>; 154 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&clocks BCM2835_CLOCK_UART>, 156 <&clocks BCM2835_CLOCK_VPU>; 157 clock-names = "uartclk", "apb_pclk"; 158 arm,primecell-periphid = <0x00241011>; 159 status = "disabled"; 160 }; 161 162 uart5: serial@7e201a00 { 163 compatible = "arm,pl011", "arm,primecell"; 164 reg = <0x7e201a00 0x200>; 165 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 166 clocks = <&clocks BCM2835_CLOCK_UART>, 167 <&clocks BCM2835_CLOCK_VPU>; 168 clock-names = "uartclk", "apb_pclk"; 169 arm,primecell-periphid = <0x00241011>; 170 status = "disabled"; 171 }; 172 173 spi3: spi@7e204600 { 174 compatible = "brcm,bcm2835-spi"; 175 reg = <0x7e204600 0x0200>; 176 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 177 clocks = <&clocks BCM2835_CLOCK_VPU>; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 status = "disabled"; 181 }; 182 183 spi4: spi@7e204800 { 184 compatible = "brcm,bcm2835-spi"; 185 reg = <0x7e204800 0x0200>; 186 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 187 clocks = <&clocks BCM2835_CLOCK_VPU>; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 status = "disabled"; 191 }; 192 193 spi5: spi@7e204a00 { 194 compatible = "brcm,bcm2835-spi"; 195 reg = <0x7e204a00 0x0200>; 196 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&clocks BCM2835_CLOCK_VPU>; 198 #address-cells = <1>; 199 #size-cells = <0>; 200 status = "disabled"; 201 }; 202 203 spi6: spi@7e204c00 { 204 compatible = "brcm,bcm2835-spi"; 205 reg = <0x7e204c00 0x0200>; 206 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&clocks BCM2835_CLOCK_VPU>; 208 #address-cells = <1>; 209 #size-cells = <0>; 210 status = "disabled"; 211 }; 212 213 i2c3: i2c@7e205600 { 214 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 215 reg = <0x7e205600 0x200>; 216 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&clocks BCM2835_CLOCK_VPU>; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 status = "disabled"; 221 }; 222 223 i2c4: i2c@7e205800 { 224 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 225 reg = <0x7e205800 0x200>; 226 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&clocks BCM2835_CLOCK_VPU>; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 status = "disabled"; 231 }; 232 233 i2c5: i2c@7e205a00 { 234 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 235 reg = <0x7e205a00 0x200>; 236 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&clocks BCM2835_CLOCK_VPU>; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 status = "disabled"; 241 }; 242 243 i2c6: i2c@7e205c00 { 244 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 245 reg = <0x7e205c00 0x200>; 246 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&clocks BCM2835_CLOCK_VPU>; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 status = "disabled"; 251 }; 252 253 pixelvalve0: pixelvalve@7e206000 { 254 compatible = "brcm,bcm2711-pixelvalve0"; 255 reg = <0x7e206000 0x100>; 256 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 257 status = "disabled"; 258 }; 259 260 pixelvalve1: pixelvalve@7e207000 { 261 compatible = "brcm,bcm2711-pixelvalve1"; 262 reg = <0x7e207000 0x100>; 263 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 264 status = "disabled"; 265 }; 266 267 pixelvalve2: pixelvalve@7e20a000 { 268 compatible = "brcm,bcm2711-pixelvalve2"; 269 reg = <0x7e20a000 0x100>; 270 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 271 status = "disabled"; 272 }; 273 274 pwm1: pwm@7e20c800 { 275 compatible = "brcm,bcm2835-pwm"; 276 reg = <0x7e20c800 0x28>; 277 clocks = <&clocks BCM2835_CLOCK_PWM>; 278 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; 279 assigned-clock-rates = <10000000>; 280 #pwm-cells = <2>; 281 status = "disabled"; 282 }; 283 284 pixelvalve4: pixelvalve@7e216000 { 285 compatible = "brcm,bcm2711-pixelvalve4"; 286 reg = <0x7e216000 0x100>; 287 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 288 status = "disabled"; 289 }; 290 291 hvs: hvs@7e400000 { 292 compatible = "brcm,bcm2711-hvs"; 293 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 294 }; 295 296 pixelvalve3: pixelvalve@7ec12000 { 297 compatible = "brcm,bcm2711-pixelvalve3"; 298 reg = <0x7ec12000 0x100>; 299 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 300 status = "disabled"; 301 }; 302 303 vec: vec@7ec13000 { 304 compatible = "brcm,bcm2711-vec"; 305 reg = <0x7ec13000 0x1000>; 306 clocks = <&clocks BCM2835_CLOCK_VEC>; 307 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 308 status = "disabled"; 309 }; 310 311 dvp: clock@7ef00000 { 312 compatible = "brcm,brcm2711-dvp"; 313 reg = <0x7ef00000 0x10>; 314 clocks = <&clk_108MHz>; 315 #clock-cells = <1>; 316 #reset-cells = <1>; 317 }; 318 319 aon_intr: interrupt-controller@7ef00100 { 320 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; 321 reg = <0x7ef00100 0x30>; 322 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 323 interrupt-controller; 324 #interrupt-cells = <1>; 325 }; 326 327 hdmi0: hdmi@7ef00700 { 328 compatible = "brcm,bcm2711-hdmi0"; 329 reg = <0x7ef00700 0x300>, 330 <0x7ef00300 0x200>, 331 <0x7ef00f00 0x80>, 332 <0x7ef00f80 0x80>, 333 <0x7ef01b00 0x200>, 334 <0x7ef01f00 0x400>, 335 <0x7ef00200 0x80>, 336 <0x7ef04300 0x100>, 337 <0x7ef20000 0x100>; 338 reg-names = "hdmi", 339 "dvp", 340 "phy", 341 "rm", 342 "packet", 343 "metadata", 344 "csc", 345 "cec", 346 "hd"; 347 clock-names = "hdmi", "bvb", "audio", "cec"; 348 resets = <&dvp 0>; 349 interrupt-parent = <&aon_intr>; 350 interrupts = <0>, <1>, <2>, 351 <3>, <4>, <5>; 352 interrupt-names = "cec-tx", "cec-rx", "cec-low", 353 "wakeup", "hpd-connected", "hpd-removed"; 354 ddc = <&ddc0>; 355 dmas = <&dma 10>; 356 dma-names = "audio-rx"; 357 status = "disabled"; 358 }; 359 360 ddc0: i2c@7ef04500 { 361 compatible = "brcm,bcm2711-hdmi-i2c"; 362 reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>; 363 reg-names = "bsc", "auto-i2c"; 364 clock-frequency = <97500>; 365 status = "disabled"; 366 }; 367 368 hdmi1: hdmi@7ef05700 { 369 compatible = "brcm,bcm2711-hdmi1"; 370 reg = <0x7ef05700 0x300>, 371 <0x7ef05300 0x200>, 372 <0x7ef05f00 0x80>, 373 <0x7ef05f80 0x80>, 374 <0x7ef06b00 0x200>, 375 <0x7ef06f00 0x400>, 376 <0x7ef00280 0x80>, 377 <0x7ef09300 0x100>, 378 <0x7ef20000 0x100>; 379 reg-names = "hdmi", 380 "dvp", 381 "phy", 382 "rm", 383 "packet", 384 "metadata", 385 "csc", 386 "cec", 387 "hd"; 388 ddc = <&ddc1>; 389 clock-names = "hdmi", "bvb", "audio", "cec"; 390 resets = <&dvp 1>; 391 interrupt-parent = <&aon_intr>; 392 interrupts = <8>, <7>, <6>, 393 <9>, <10>, <11>; 394 interrupt-names = "cec-tx", "cec-rx", "cec-low", 395 "wakeup", "hpd-connected", "hpd-removed"; 396 dmas = <&dma 17>; 397 dma-names = "audio-rx"; 398 status = "disabled"; 399 }; 400 401 ddc1: i2c@7ef09500 { 402 compatible = "brcm,bcm2711-hdmi-i2c"; 403 reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>; 404 reg-names = "bsc", "auto-i2c"; 405 clock-frequency = <97500>; 406 status = "disabled"; 407 }; 408 }; 409 410 /* 411 * emmc2 has different DMA constraints based on SoC revisions. It was 412 * moved into its own bus, so as for RPi4's firmware to update them. 413 * The firmware will find whether the emmc2bus alias is defined, and if 414 * so, it'll edit the dma-ranges property below accordingly. 415 */ 416 emmc2bus: emmc2bus { 417 compatible = "simple-bus"; 418 #address-cells = <2>; 419 #size-cells = <1>; 420 421 ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>; 422 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>; 423 424 emmc2: mmc@7e340000 { 425 compatible = "brcm,bcm2711-emmc2"; 426 reg = <0x0 0x7e340000 0x100>; 427 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&clocks BCM2711_CLOCK_EMMC2>; 429 status = "disabled"; 430 }; 431 }; 432 433 arm-pmu { 434 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3"; 435 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 439 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 440 }; 441 442 timer { 443 compatible = "arm,armv8-timer"; 444 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 445 IRQ_TYPE_LEVEL_LOW)>, 446 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 447 IRQ_TYPE_LEVEL_LOW)>, 448 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 449 IRQ_TYPE_LEVEL_LOW)>, 450 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 451 IRQ_TYPE_LEVEL_LOW)>; 452 /* This only applies to the ARMv7 stub */ 453 arm,cpu-registers-not-fw-configured; 454 }; 455 456 cpus: cpus { 457 #address-cells = <1>; 458 #size-cells = <0>; 459 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit 460 461 cpu0: cpu@0 { 462 device_type = "cpu"; 463 compatible = "arm,cortex-a72"; 464 reg = <0>; 465 enable-method = "spin-table"; 466 cpu-release-addr = <0x0 0x000000d8>; 467 }; 468 469 cpu1: cpu@1 { 470 device_type = "cpu"; 471 compatible = "arm,cortex-a72"; 472 reg = <1>; 473 enable-method = "spin-table"; 474 cpu-release-addr = <0x0 0x000000e0>; 475 }; 476 477 cpu2: cpu@2 { 478 device_type = "cpu"; 479 compatible = "arm,cortex-a72"; 480 reg = <2>; 481 enable-method = "spin-table"; 482 cpu-release-addr = <0x0 0x000000e8>; 483 }; 484 485 cpu3: cpu@3 { 486 device_type = "cpu"; 487 compatible = "arm,cortex-a72"; 488 reg = <3>; 489 enable-method = "spin-table"; 490 cpu-release-addr = <0x0 0x000000f0>; 491 }; 492 }; 493 494 scb { 495 compatible = "simple-bus"; 496 #address-cells = <2>; 497 #size-cells = <1>; 498 499 ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>, 500 <0x6 0x00000000 0x6 0x00000000 0x40000000>; 501 502 pcie0: pcie@7d500000 { 503 compatible = "brcm,bcm2711-pcie"; 504 reg = <0x0 0x7d500000 0x9310>; 505 device_type = "pci"; 506 #address-cells = <3>; 507 #interrupt-cells = <1>; 508 #size-cells = <2>; 509 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 511 interrupt-names = "pcie", "msi"; 512 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 513 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 514 IRQ_TYPE_LEVEL_HIGH>, 515 <0 0 0 2 &gicv2 GIC_SPI 144 516 IRQ_TYPE_LEVEL_HIGH>, 517 <0 0 0 3 &gicv2 GIC_SPI 145 518 IRQ_TYPE_LEVEL_HIGH>, 519 <0 0 0 4 &gicv2 GIC_SPI 146 520 IRQ_TYPE_LEVEL_HIGH>; 521 msi-controller; 522 msi-parent = <&pcie0>; 523 524 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 525 0x0 0x04000000>; 526 /* 527 * The wrapper around the PCIe block has a bug 528 * preventing it from accessing beyond the first 3GB of 529 * memory. 530 */ 531 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 532 0x0 0xc0000000>; 533 brcm,enable-ssc; 534 }; 535 536 genet: ethernet@7d580000 { 537 compatible = "brcm,bcm2711-genet-v5"; 538 reg = <0x0 0x7d580000 0x10000>; 539 #address-cells = <0x1>; 540 #size-cells = <0x1>; 541 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 543 status = "disabled"; 544 545 genet_mdio: mdio@e14 { 546 compatible = "brcm,genet-mdio-v5"; 547 reg = <0xe14 0x8>; 548 reg-names = "mdio"; 549 #address-cells = <0x1>; 550 #size-cells = <0x0>; 551 }; 552 }; 553 }; 554}; 555 556&clk_osc { 557 clock-frequency = <54000000>; 558}; 559 560&clocks { 561 compatible = "brcm,bcm2711-cprman"; 562}; 563 564&cpu_thermal { 565 coefficients = <(-487) 410040>; 566 thermal-sensors = <&thermal>; 567}; 568 569&dsi0 { 570 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 571}; 572 573&dsi1 { 574 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 575 compatible = "brcm,bcm2711-dsi1"; 576}; 577 578&gpio { 579 compatible = "brcm,bcm2711-gpio"; 580 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 584 585 gpio-ranges = <&gpio 0 0 58>; 586 587 gpclk0_gpio49: gpclk0_gpio49 { 588 pin-gpclk { 589 pins = "gpio49"; 590 function = "alt1"; 591 bias-disable; 592 }; 593 }; 594 gpclk1_gpio50: gpclk1_gpio50 { 595 pin-gpclk { 596 pins = "gpio50"; 597 function = "alt1"; 598 bias-disable; 599 }; 600 }; 601 gpclk2_gpio51: gpclk2_gpio51 { 602 pin-gpclk { 603 pins = "gpio51"; 604 function = "alt1"; 605 bias-disable; 606 }; 607 }; 608 609 i2c0_gpio46: i2c0_gpio46 { 610 pin-sda { 611 function = "alt0"; 612 pins = "gpio46"; 613 bias-pull-up; 614 }; 615 pin-scl { 616 function = "alt0"; 617 pins = "gpio47"; 618 bias-disable; 619 }; 620 }; 621 i2c1_gpio46: i2c1_gpio46 { 622 pin-sda { 623 function = "alt1"; 624 pins = "gpio46"; 625 bias-pull-up; 626 }; 627 pin-scl { 628 function = "alt1"; 629 pins = "gpio47"; 630 bias-disable; 631 }; 632 }; 633 i2c3_gpio2: i2c3_gpio2 { 634 pin-sda { 635 function = "alt5"; 636 pins = "gpio2"; 637 bias-pull-up; 638 }; 639 pin-scl { 640 function = "alt5"; 641 pins = "gpio3"; 642 bias-disable; 643 }; 644 }; 645 i2c3_gpio4: i2c3_gpio4 { 646 pin-sda { 647 function = "alt5"; 648 pins = "gpio4"; 649 bias-pull-up; 650 }; 651 pin-scl { 652 function = "alt5"; 653 pins = "gpio5"; 654 bias-disable; 655 }; 656 }; 657 i2c4_gpio6: i2c4_gpio6 { 658 pin-sda { 659 function = "alt5"; 660 pins = "gpio6"; 661 bias-pull-up; 662 }; 663 pin-scl { 664 function = "alt5"; 665 pins = "gpio7"; 666 bias-disable; 667 }; 668 }; 669 i2c4_gpio8: i2c4_gpio8 { 670 pin-sda { 671 function = "alt5"; 672 pins = "gpio8"; 673 bias-pull-up; 674 }; 675 pin-scl { 676 function = "alt5"; 677 pins = "gpio9"; 678 bias-disable; 679 }; 680 }; 681 i2c5_gpio10: i2c5_gpio10 { 682 pin-sda { 683 function = "alt5"; 684 pins = "gpio10"; 685 bias-pull-up; 686 }; 687 pin-scl { 688 function = "alt5"; 689 pins = "gpio11"; 690 bias-disable; 691 }; 692 }; 693 i2c5_gpio12: i2c5_gpio12 { 694 pin-sda { 695 function = "alt5"; 696 pins = "gpio12"; 697 bias-pull-up; 698 }; 699 pin-scl { 700 function = "alt5"; 701 pins = "gpio13"; 702 bias-disable; 703 }; 704 }; 705 i2c6_gpio0: i2c6_gpio0 { 706 pin-sda { 707 function = "alt5"; 708 pins = "gpio0"; 709 bias-pull-up; 710 }; 711 pin-scl { 712 function = "alt5"; 713 pins = "gpio1"; 714 bias-disable; 715 }; 716 }; 717 i2c6_gpio22: i2c6_gpio22 { 718 pin-sda { 719 function = "alt5"; 720 pins = "gpio22"; 721 bias-pull-up; 722 }; 723 pin-scl { 724 function = "alt5"; 725 pins = "gpio23"; 726 bias-disable; 727 }; 728 }; 729 i2c_slave_gpio8: i2c_slave_gpio8 { 730 pins-i2c-slave { 731 pins = "gpio8", 732 "gpio9", 733 "gpio10", 734 "gpio11"; 735 function = "alt3"; 736 }; 737 }; 738 739 jtag_gpio48: jtag_gpio48 { 740 pins-jtag { 741 pins = "gpio48", 742 "gpio49", 743 "gpio50", 744 "gpio51", 745 "gpio52", 746 "gpio53"; 747 function = "alt4"; 748 }; 749 }; 750 751 mii_gpio28: mii_gpio28 { 752 pins-mii { 753 pins = "gpio28", 754 "gpio29", 755 "gpio30", 756 "gpio31"; 757 function = "alt4"; 758 }; 759 }; 760 mii_gpio36: mii_gpio36 { 761 pins-mii { 762 pins = "gpio36", 763 "gpio37", 764 "gpio38", 765 "gpio39"; 766 function = "alt5"; 767 }; 768 }; 769 770 pcm_gpio50: pcm_gpio50 { 771 pins-pcm { 772 pins = "gpio50", 773 "gpio51", 774 "gpio52", 775 "gpio53"; 776 function = "alt2"; 777 }; 778 }; 779 780 pwm0_0_gpio12: pwm0_0_gpio12 { 781 pin-pwm { 782 pins = "gpio12"; 783 function = "alt0"; 784 bias-disable; 785 }; 786 }; 787 pwm0_0_gpio18: pwm0_0_gpio18 { 788 pin-pwm { 789 pins = "gpio18"; 790 function = "alt5"; 791 bias-disable; 792 }; 793 }; 794 pwm1_0_gpio40: pwm1_0_gpio40 { 795 pin-pwm { 796 pins = "gpio40"; 797 function = "alt0"; 798 bias-disable; 799 }; 800 }; 801 pwm0_1_gpio13: pwm0_1_gpio13 { 802 pin-pwm { 803 pins = "gpio13"; 804 function = "alt0"; 805 bias-disable; 806 }; 807 }; 808 pwm0_1_gpio19: pwm0_1_gpio19 { 809 pin-pwm { 810 pins = "gpio19"; 811 function = "alt5"; 812 bias-disable; 813 }; 814 }; 815 pwm1_1_gpio41: pwm1_1_gpio41 { 816 pin-pwm { 817 pins = "gpio41"; 818 function = "alt0"; 819 bias-disable; 820 }; 821 }; 822 pwm0_1_gpio45: pwm0_1_gpio45 { 823 pin-pwm { 824 pins = "gpio45"; 825 function = "alt0"; 826 bias-disable; 827 }; 828 }; 829 pwm0_0_gpio52: pwm0_0_gpio52 { 830 pin-pwm { 831 pins = "gpio52"; 832 function = "alt1"; 833 bias-disable; 834 }; 835 }; 836 pwm0_1_gpio53: pwm0_1_gpio53 { 837 pin-pwm { 838 pins = "gpio53"; 839 function = "alt1"; 840 bias-disable; 841 }; 842 }; 843 844 rgmii_gpio35: rgmii_gpio35 { 845 pin-start-stop { 846 pins = "gpio35"; 847 function = "alt4"; 848 }; 849 pin-rx-ok { 850 pins = "gpio36"; 851 function = "alt4"; 852 }; 853 }; 854 rgmii_irq_gpio34: rgmii_irq_gpio34 { 855 pin-irq { 856 pins = "gpio34"; 857 function = "alt5"; 858 }; 859 }; 860 rgmii_irq_gpio39: rgmii_irq_gpio39 { 861 pin-irq { 862 pins = "gpio39"; 863 function = "alt4"; 864 }; 865 }; 866 rgmii_mdio_gpio28: rgmii_mdio_gpio28 { 867 pins-mdio { 868 pins = "gpio28", 869 "gpio29"; 870 function = "alt5"; 871 }; 872 }; 873 rgmii_mdio_gpio37: rgmii_mdio_gpio37 { 874 pins-mdio { 875 pins = "gpio37", 876 "gpio38"; 877 function = "alt4"; 878 }; 879 }; 880 881 spi0_gpio46: spi0_gpio46 { 882 pins-spi { 883 pins = "gpio46", 884 "gpio47", 885 "gpio48", 886 "gpio49"; 887 function = "alt2"; 888 }; 889 }; 890 spi2_gpio46: spi2_gpio46 { 891 pins-spi { 892 pins = "gpio46", 893 "gpio47", 894 "gpio48", 895 "gpio49", 896 "gpio50"; 897 function = "alt5"; 898 }; 899 }; 900 spi3_gpio0: spi3_gpio0 { 901 pins-spi { 902 pins = "gpio0", 903 "gpio1", 904 "gpio2", 905 "gpio3"; 906 function = "alt3"; 907 }; 908 }; 909 spi4_gpio4: spi4_gpio4 { 910 pins-spi { 911 pins = "gpio4", 912 "gpio5", 913 "gpio6", 914 "gpio7"; 915 function = "alt3"; 916 }; 917 }; 918 spi5_gpio12: spi5_gpio12 { 919 pins-spi { 920 pins = "gpio12", 921 "gpio13", 922 "gpio14", 923 "gpio15"; 924 function = "alt3"; 925 }; 926 }; 927 spi6_gpio18: spi6_gpio18 { 928 pins-spi { 929 pins = "gpio18", 930 "gpio19", 931 "gpio20", 932 "gpio21"; 933 function = "alt3"; 934 }; 935 }; 936 937 uart2_gpio0: uart2_gpio0 { 938 pin-tx { 939 pins = "gpio0"; 940 function = "alt4"; 941 bias-disable; 942 }; 943 pin-rx { 944 pins = "gpio1"; 945 function = "alt4"; 946 bias-pull-up; 947 }; 948 }; 949 uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 { 950 pin-cts { 951 pins = "gpio2"; 952 function = "alt4"; 953 bias-pull-up; 954 }; 955 pin-rts { 956 pins = "gpio3"; 957 function = "alt4"; 958 bias-disable; 959 }; 960 }; 961 uart3_gpio4: uart3_gpio4 { 962 pin-tx { 963 pins = "gpio4"; 964 function = "alt4"; 965 bias-disable; 966 }; 967 pin-rx { 968 pins = "gpio5"; 969 function = "alt4"; 970 bias-pull-up; 971 }; 972 }; 973 uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 { 974 pin-cts { 975 pins = "gpio6"; 976 function = "alt4"; 977 bias-pull-up; 978 }; 979 pin-rts { 980 pins = "gpio7"; 981 function = "alt4"; 982 bias-disable; 983 }; 984 }; 985 uart4_gpio8: uart4_gpio8 { 986 pin-tx { 987 pins = "gpio8"; 988 function = "alt4"; 989 bias-disable; 990 }; 991 pin-rx { 992 pins = "gpio9"; 993 function = "alt4"; 994 bias-pull-up; 995 }; 996 }; 997 uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 { 998 pin-cts { 999 pins = "gpio10"; 1000 function = "alt4"; 1001 bias-pull-up; 1002 }; 1003 pin-rts { 1004 pins = "gpio11"; 1005 function = "alt4"; 1006 bias-disable; 1007 }; 1008 }; 1009 uart5_gpio12: uart5_gpio12 { 1010 pin-tx { 1011 pins = "gpio12"; 1012 function = "alt4"; 1013 bias-disable; 1014 }; 1015 pin-rx { 1016 pins = "gpio13"; 1017 function = "alt4"; 1018 bias-pull-up; 1019 }; 1020 }; 1021 uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 { 1022 pin-cts { 1023 pins = "gpio14"; 1024 function = "alt4"; 1025 bias-pull-up; 1026 }; 1027 pin-rts { 1028 pins = "gpio15"; 1029 function = "alt4"; 1030 bias-disable; 1031 }; 1032 }; 1033}; 1034 1035&rmem { 1036 #address-cells = <2>; 1037}; 1038 1039&cma { 1040 /* 1041 * arm64 reserves the CMA by default somewhere in ZONE_DMA32, 1042 * that's not good enough for the BCM2711 as some devices can 1043 * only address the lower 1G of memory (ZONE_DMA). 1044 */ 1045 alloc-ranges = <0x0 0x00000000 0x40000000>; 1046}; 1047 1048&i2c0 { 1049 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 1050 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1051}; 1052 1053&i2c1 { 1054 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 1055 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1056}; 1057 1058&mailbox { 1059 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1060}; 1061 1062&sdhci { 1063 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1064}; 1065 1066&sdhost { 1067 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1068}; 1069 1070&spi { 1071 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1072}; 1073 1074&spi1 { 1075 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1076}; 1077 1078&spi2 { 1079 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1080}; 1081 1082&system_timer { 1083 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1087}; 1088 1089&txp { 1090 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1091}; 1092 1093&uart0 { 1094 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1095}; 1096 1097&uart1 { 1098 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1099}; 1100 1101&usb { 1102 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1103}; 1104 1105&vec { 1106 compatible = "brcm,bcm2711-vec"; 1107 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1108}; 1109