1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung Exynos5250 SoC device tree source 4 * 5 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 * 8 * Samsung Exynos5250 SoC device nodes are listed in this file. 9 * Exynos5250 based board files can include this file and provide 10 * values for board specfic bindings. 11 * 12 * Note: This file does not include device nodes for all the controllers in 13 * Exynos5250 SoC. As device tree coverage for Exynos5250 increases, 14 * additional nodes can be added to this file. 15 */ 16 17#include <dt-bindings/clock/exynos5250.h> 18#include "exynos5.dtsi" 19#include "exynos4-cpu-thermal.dtsi" 20#include <dt-bindings/clock/exynos-audss-clk.h> 21 22/ { 23 compatible = "samsung,exynos5250", "samsung,exynos5"; 24 25 aliases { 26 spi0 = &spi_0; 27 spi1 = &spi_1; 28 spi2 = &spi_2; 29 gsc0 = &gsc_0; 30 gsc1 = &gsc_1; 31 gsc2 = &gsc_2; 32 gsc3 = &gsc_3; 33 mshc0 = &mmc_0; 34 mshc1 = &mmc_1; 35 mshc2 = &mmc_2; 36 mshc3 = &mmc_3; 37 i2c4 = &i2c_4; 38 i2c5 = &i2c_5; 39 i2c6 = &i2c_6; 40 i2c7 = &i2c_7; 41 i2c8 = &i2c_8; 42 i2c9 = &i2c_9; 43 pinctrl0 = &pinctrl_0; 44 pinctrl1 = &pinctrl_1; 45 pinctrl2 = &pinctrl_2; 46 pinctrl3 = &pinctrl_3; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu-map { 54 cluster0 { 55 core0 { 56 cpu = <&cpu0>; 57 }; 58 core1 { 59 cpu = <&cpu1>; 60 }; 61 }; 62 }; 63 64 cpu0: cpu@0 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a15"; 67 reg = <0>; 68 clocks = <&clock CLK_ARM_CLK>; 69 clock-names = "cpu"; 70 operating-points-v2 = <&cpu0_opp_table>; 71 #cooling-cells = <2>; /* min followed by max */ 72 }; 73 cpu1: cpu@1 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a15"; 76 reg = <1>; 77 clocks = <&clock CLK_ARM_CLK>; 78 clock-names = "cpu"; 79 operating-points-v2 = <&cpu0_opp_table>; 80 #cooling-cells = <2>; /* min followed by max */ 81 }; 82 }; 83 84 cpu0_opp_table: opp-table0 { 85 compatible = "operating-points-v2"; 86 opp-shared; 87 88 opp-200000000 { 89 opp-hz = /bits/ 64 <200000000>; 90 opp-microvolt = <925000>; 91 clock-latency-ns = <140000>; 92 }; 93 opp-300000000 { 94 opp-hz = /bits/ 64 <300000000>; 95 opp-microvolt = <937500>; 96 clock-latency-ns = <140000>; 97 }; 98 opp-400000000 { 99 opp-hz = /bits/ 64 <400000000>; 100 opp-microvolt = <950000>; 101 clock-latency-ns = <140000>; 102 }; 103 opp-500000000 { 104 opp-hz = /bits/ 64 <500000000>; 105 opp-microvolt = <975000>; 106 clock-latency-ns = <140000>; 107 }; 108 opp-600000000 { 109 opp-hz = /bits/ 64 <600000000>; 110 opp-microvolt = <1000000>; 111 clock-latency-ns = <140000>; 112 }; 113 opp-700000000 { 114 opp-hz = /bits/ 64 <700000000>; 115 opp-microvolt = <1012500>; 116 clock-latency-ns = <140000>; 117 }; 118 opp-800000000 { 119 opp-hz = /bits/ 64 <800000000>; 120 opp-microvolt = <1025000>; 121 clock-latency-ns = <140000>; 122 }; 123 opp-900000000 { 124 opp-hz = /bits/ 64 <900000000>; 125 opp-microvolt = <1050000>; 126 clock-latency-ns = <140000>; 127 }; 128 opp-1000000000 { 129 opp-hz = /bits/ 64 <1000000000>; 130 opp-microvolt = <1075000>; 131 clock-latency-ns = <140000>; 132 opp-suspend; 133 }; 134 opp-1100000000 { 135 opp-hz = /bits/ 64 <1100000000>; 136 opp-microvolt = <1100000>; 137 clock-latency-ns = <140000>; 138 }; 139 opp-1200000000 { 140 opp-hz = /bits/ 64 <1200000000>; 141 opp-microvolt = <1125000>; 142 clock-latency-ns = <140000>; 143 }; 144 opp-1300000000 { 145 opp-hz = /bits/ 64 <1300000000>; 146 opp-microvolt = <1150000>; 147 clock-latency-ns = <140000>; 148 }; 149 opp-1400000000 { 150 opp-hz = /bits/ 64 <1400000000>; 151 opp-microvolt = <1200000>; 152 clock-latency-ns = <140000>; 153 }; 154 opp-1500000000 { 155 opp-hz = /bits/ 64 <1500000000>; 156 opp-microvolt = <1225000>; 157 clock-latency-ns = <140000>; 158 }; 159 opp-1600000000 { 160 opp-hz = /bits/ 64 <1600000000>; 161 opp-microvolt = <1250000>; 162 clock-latency-ns = <140000>; 163 }; 164 opp-1700000000 { 165 opp-hz = /bits/ 64 <1700000000>; 166 opp-microvolt = <1300000>; 167 clock-latency-ns = <140000>; 168 }; 169 }; 170 171 pmu { 172 compatible = "arm,cortex-a15-pmu"; 173 interrupt-parent = <&combiner>; 174 interrupts = <1 2>, <22 4>; 175 }; 176 177 soc: soc { 178 sram@2020000 { 179 compatible = "mmio-sram"; 180 reg = <0x02020000 0x30000>; 181 #address-cells = <1>; 182 #size-cells = <1>; 183 ranges = <0 0x02020000 0x30000>; 184 185 smp-sram@0 { 186 compatible = "samsung,exynos4210-sysram"; 187 reg = <0x0 0x1000>; 188 }; 189 190 smp-sram@2f000 { 191 compatible = "samsung,exynos4210-sysram-ns"; 192 reg = <0x2f000 0x1000>; 193 }; 194 }; 195 196 pd_gsc: power-domain@10044000 { 197 compatible = "samsung,exynos4210-pd"; 198 reg = <0x10044000 0x20>; 199 #power-domain-cells = <0>; 200 label = "GSC"; 201 }; 202 203 pd_mfc: power-domain@10044040 { 204 compatible = "samsung,exynos4210-pd"; 205 reg = <0x10044040 0x20>; 206 #power-domain-cells = <0>; 207 label = "MFC"; 208 }; 209 210 pd_g3d: power-domain@10044060 { 211 compatible = "samsung,exynos4210-pd"; 212 reg = <0x10044060 0x20>; 213 #power-domain-cells = <0>; 214 label = "G3D"; 215 }; 216 217 pd_disp1: power-domain@100440a0 { 218 compatible = "samsung,exynos4210-pd"; 219 reg = <0x100440A0 0x20>; 220 #power-domain-cells = <0>; 221 label = "DISP1"; 222 }; 223 224 pd_mau: power-domain@100440c0 { 225 compatible = "samsung,exynos4210-pd"; 226 reg = <0x100440C0 0x20>; 227 #power-domain-cells = <0>; 228 label = "MAU"; 229 }; 230 231 clock: clock-controller@10010000 { 232 compatible = "samsung,exynos5250-clock"; 233 reg = <0x10010000 0x30000>; 234 #clock-cells = <1>; 235 }; 236 237 clock_audss: audss-clock-controller@3810000 { 238 compatible = "samsung,exynos5250-audss-clock"; 239 reg = <0x03810000 0x0C>; 240 #clock-cells = <1>; 241 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, 242 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; 243 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; 244 power-domains = <&pd_mau>; 245 }; 246 247 timer@101c0000 { 248 compatible = "samsung,exynos4210-mct"; 249 reg = <0x101C0000 0x800>; 250 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 251 clock-names = "fin_pll", "mct"; 252 interrupts-extended = <&combiner 23 3>, 253 <&combiner 23 4>, 254 <&combiner 25 2>, 255 <&combiner 25 3>, 256 <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 257 <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 258 }; 259 260 pinctrl_0: pinctrl@11400000 { 261 compatible = "samsung,exynos5250-pinctrl"; 262 reg = <0x11400000 0x1000>; 263 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 264 265 wakup_eint: wakeup-interrupt-controller { 266 compatible = "samsung,exynos4210-wakeup-eint"; 267 interrupt-parent = <&gic>; 268 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 269 }; 270 }; 271 272 pinctrl_1: pinctrl@13400000 { 273 compatible = "samsung,exynos5250-pinctrl"; 274 reg = <0x13400000 0x1000>; 275 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 276 }; 277 278 pinctrl_2: pinctrl@10d10000 { 279 compatible = "samsung,exynos5250-pinctrl"; 280 reg = <0x10d10000 0x1000>; 281 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 282 }; 283 284 pinctrl_3: pinctrl@3860000 { 285 compatible = "samsung,exynos5250-pinctrl"; 286 reg = <0x03860000 0x1000>; 287 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 288 power-domains = <&pd_mau>; 289 }; 290 291 pmu_system_controller: system-controller@10040000 { 292 compatible = "samsung,exynos5250-pmu", "syscon"; 293 reg = <0x10040000 0x5000>; 294 clock-names = "clkout16"; 295 clocks = <&clock CLK_FIN_PLL>; 296 #clock-cells = <1>; 297 interrupt-controller; 298 #interrupt-cells = <3>; 299 interrupt-parent = <&gic>; 300 }; 301 302 watchdog@101d0000 { 303 compatible = "samsung,exynos5250-wdt"; 304 reg = <0x101D0000 0x100>; 305 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&clock CLK_WDT>; 307 clock-names = "watchdog"; 308 samsung,syscon-phandle = <&pmu_system_controller>; 309 }; 310 311 mfc: codec@11000000 { 312 compatible = "samsung,mfc-v6"; 313 reg = <0x11000000 0x10000>; 314 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 315 power-domains = <&pd_mfc>; 316 clocks = <&clock CLK_MFC>; 317 clock-names = "mfc"; 318 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; 319 iommu-names = "left", "right"; 320 }; 321 322 rotator: rotator@11c00000 { 323 compatible = "samsung,exynos5250-rotator"; 324 reg = <0x11C00000 0x64>; 325 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&clock CLK_ROTATOR>; 327 clock-names = "rotator"; 328 iommus = <&sysmmu_rotator>; 329 }; 330 331 mali: gpu@11800000 { 332 compatible = "samsung,exynos5250-mali", "arm,mali-t604"; 333 reg = <0x11800000 0x5000>; 334 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 337 interrupt-names = "job", "mmu", "gpu"; 338 clocks = <&clock CLK_G3D>; 339 clock-names = "core"; 340 operating-points-v2 = <&gpu_opp_table>; 341 power-domains = <&pd_g3d>; 342 status = "disabled"; 343 344 gpu_opp_table: opp-table { 345 compatible = "operating-points-v2"; 346 347 opp-100000000 { 348 opp-hz = /bits/ 64 <100000000>; 349 opp-microvolt = <925000>; 350 }; 351 opp-160000000 { 352 opp-hz = /bits/ 64 <160000000>; 353 opp-microvolt = <925000>; 354 }; 355 opp-266000000 { 356 opp-hz = /bits/ 64 <266000000>; 357 opp-microvolt = <1025000>; 358 }; 359 opp-350000000 { 360 opp-hz = /bits/ 64 <350000000>; 361 opp-microvolt = <1075000>; 362 }; 363 opp-400000000 { 364 opp-hz = /bits/ 64 <400000000>; 365 opp-microvolt = <1125000>; 366 }; 367 opp-450000000 { 368 opp-hz = /bits/ 64 <450000000>; 369 opp-microvolt = <1150000>; 370 }; 371 opp-533000000 { 372 opp-hz = /bits/ 64 <533000000>; 373 opp-microvolt = <1250000>; 374 }; 375 }; 376 }; 377 378 tmu: tmu@10060000 { 379 compatible = "samsung,exynos5250-tmu"; 380 reg = <0x10060000 0x100>; 381 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&clock CLK_TMU>; 383 clock-names = "tmu_apbif"; 384 #thermal-sensor-cells = <0>; 385 }; 386 387 sata: sata@122f0000 { 388 compatible = "snps,dwc-ahci"; 389 reg = <0x122F0000 0x1ff>; 390 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; 392 clock-names = "sata", "sclk_sata"; 393 phys = <&sata_phy>; 394 phy-names = "sata-phy"; 395 ports-implemented = <0x1>; 396 status = "disabled"; 397 }; 398 399 sata_phy: sata-phy@12170000 { 400 compatible = "samsung,exynos5250-sata-phy"; 401 reg = <0x12170000 0x1ff>; 402 clocks = <&clock CLK_SATA_PHYCTRL>; 403 clock-names = "sata_phyctrl"; 404 #phy-cells = <0>; 405 samsung,syscon-phandle = <&pmu_system_controller>; 406 status = "disabled"; 407 }; 408 409 /* i2c_0-3 are defined in exynos5.dtsi */ 410 i2c_4: i2c@12ca0000 { 411 compatible = "samsung,s3c2440-i2c"; 412 reg = <0x12CA0000 0x100>; 413 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 clocks = <&clock CLK_I2C4>; 417 clock-names = "i2c"; 418 pinctrl-names = "default"; 419 pinctrl-0 = <&i2c4_bus>; 420 status = "disabled"; 421 }; 422 423 i2c_5: i2c@12cb0000 { 424 compatible = "samsung,s3c2440-i2c"; 425 reg = <0x12CB0000 0x100>; 426 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 clocks = <&clock CLK_I2C5>; 430 clock-names = "i2c"; 431 pinctrl-names = "default"; 432 pinctrl-0 = <&i2c5_bus>; 433 status = "disabled"; 434 }; 435 436 i2c_6: i2c@12cc0000 { 437 compatible = "samsung,s3c2440-i2c"; 438 reg = <0x12CC0000 0x100>; 439 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 clocks = <&clock CLK_I2C6>; 443 clock-names = "i2c"; 444 pinctrl-names = "default"; 445 pinctrl-0 = <&i2c6_bus>; 446 status = "disabled"; 447 }; 448 449 i2c_7: i2c@12cd0000 { 450 compatible = "samsung,s3c2440-i2c"; 451 reg = <0x12CD0000 0x100>; 452 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 clocks = <&clock CLK_I2C7>; 456 clock-names = "i2c"; 457 pinctrl-names = "default"; 458 pinctrl-0 = <&i2c7_bus>; 459 status = "disabled"; 460 }; 461 462 i2c_8: i2c@12ce0000 { 463 compatible = "samsung,s3c2440-hdmiphy-i2c"; 464 reg = <0x12CE0000 0x1000>; 465 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 clocks = <&clock CLK_I2C_HDMI>; 469 clock-names = "i2c"; 470 status = "disabled"; 471 472 hdmiphy: hdmiphy@38 { 473 compatible = "samsung,exynos4212-hdmiphy"; 474 reg = <0x38>; 475 }; 476 }; 477 478 i2c_9: i2c@121d0000 { 479 compatible = "samsung,exynos5-sata-phy-i2c"; 480 reg = <0x121D0000 0x100>; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 clocks = <&clock CLK_SATA_PHYI2C>; 484 clock-names = "i2c"; 485 status = "disabled"; 486 487 sata_phy_i2c: sata-phy-i2c@38 { 488 compatible = "samsung,exynos-sataphy-i2c"; 489 reg = <0x38>; 490 status = "disabled"; 491 }; 492 }; 493 494 spi_0: spi@12d20000 { 495 compatible = "samsung,exynos4210-spi"; 496 status = "disabled"; 497 reg = <0x12d20000 0x100>; 498 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 499 dmas = <&pdma0 5 500 &pdma0 4>; 501 dma-names = "tx", "rx"; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; 505 clock-names = "spi", "spi_busclk0"; 506 pinctrl-names = "default"; 507 pinctrl-0 = <&spi0_bus>; 508 }; 509 510 spi_1: spi@12d30000 { 511 compatible = "samsung,exynos4210-spi"; 512 status = "disabled"; 513 reg = <0x12d30000 0x100>; 514 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 515 dmas = <&pdma1 5 516 &pdma1 4>; 517 dma-names = "tx", "rx"; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; 521 clock-names = "spi", "spi_busclk0"; 522 pinctrl-names = "default"; 523 pinctrl-0 = <&spi1_bus>; 524 }; 525 526 spi_2: spi@12d40000 { 527 compatible = "samsung,exynos4210-spi"; 528 status = "disabled"; 529 reg = <0x12d40000 0x100>; 530 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 531 dmas = <&pdma0 7 532 &pdma0 6>; 533 dma-names = "tx", "rx"; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; 537 clock-names = "spi", "spi_busclk0"; 538 pinctrl-names = "default"; 539 pinctrl-0 = <&spi2_bus>; 540 }; 541 542 mmc_0: mmc@12200000 { 543 compatible = "samsung,exynos5250-dw-mshc"; 544 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 reg = <0x12200000 0x1000>; 548 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; 549 clock-names = "biu", "ciu"; 550 fifo-depth = <0x80>; 551 status = "disabled"; 552 }; 553 554 mmc_1: mmc@12210000 { 555 compatible = "samsung,exynos5250-dw-mshc"; 556 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 557 #address-cells = <1>; 558 #size-cells = <0>; 559 reg = <0x12210000 0x1000>; 560 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; 561 clock-names = "biu", "ciu"; 562 fifo-depth = <0x80>; 563 status = "disabled"; 564 }; 565 566 mmc_2: mmc@12220000 { 567 compatible = "samsung,exynos5250-dw-mshc"; 568 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 569 #address-cells = <1>; 570 #size-cells = <0>; 571 reg = <0x12220000 0x1000>; 572 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; 573 clock-names = "biu", "ciu"; 574 fifo-depth = <0x80>; 575 status = "disabled"; 576 }; 577 578 mmc_3: mmc@12230000 { 579 compatible = "samsung,exynos5250-dw-mshc"; 580 reg = <0x12230000 0x1000>; 581 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; 585 clock-names = "biu", "ciu"; 586 fifo-depth = <0x80>; 587 status = "disabled"; 588 }; 589 590 i2s0: i2s@3830000 { 591 compatible = "samsung,s5pv210-i2s"; 592 status = "disabled"; 593 reg = <0x03830000 0x100>; 594 dmas = <&pdma0 10>, 595 <&pdma0 9>, 596 <&pdma0 8>; 597 dma-names = "tx", "rx", "tx-sec"; 598 clocks = <&clock_audss EXYNOS_I2S_BUS>, 599 <&clock_audss EXYNOS_I2S_BUS>, 600 <&clock_audss EXYNOS_SCLK_I2S>; 601 clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 602 samsung,idma-addr = <0x03000000>; 603 pinctrl-names = "default"; 604 pinctrl-0 = <&i2s0_bus>; 605 power-domains = <&pd_mau>; 606 #clock-cells = <1>; 607 #sound-dai-cells = <1>; 608 }; 609 610 i2s1: i2s@12d60000 { 611 compatible = "samsung,s3c6410-i2s"; 612 status = "disabled"; 613 reg = <0x12D60000 0x100>; 614 dmas = <&pdma1 12>, 615 <&pdma1 11>; 616 dma-names = "tx", "rx"; 617 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; 618 clock-names = "iis", "i2s_opclk0"; 619 pinctrl-names = "default"; 620 pinctrl-0 = <&i2s1_bus>; 621 power-domains = <&pd_mau>; 622 #sound-dai-cells = <1>; 623 }; 624 625 i2s2: i2s@12d70000 { 626 compatible = "samsung,s3c6410-i2s"; 627 status = "disabled"; 628 reg = <0x12D70000 0x100>; 629 dmas = <&pdma0 12>, 630 <&pdma0 11>; 631 dma-names = "tx", "rx"; 632 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; 633 clock-names = "iis", "i2s_opclk0"; 634 pinctrl-names = "default"; 635 pinctrl-0 = <&i2s2_bus>; 636 power-domains = <&pd_mau>; 637 #sound-dai-cells = <1>; 638 }; 639 640 usb_dwc3 { 641 compatible = "samsung,exynos5250-dwusb3"; 642 clocks = <&clock CLK_USB3>; 643 clock-names = "usbdrd30"; 644 #address-cells = <1>; 645 #size-cells = <1>; 646 ranges; 647 648 usbdrd_dwc3: usb@12000000 { 649 compatible = "snps,dwc3"; 650 reg = <0x12000000 0x10000>; 651 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 652 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; 653 phy-names = "usb2-phy", "usb3-phy"; 654 }; 655 }; 656 657 usbdrd_phy: phy@12100000 { 658 compatible = "samsung,exynos5250-usbdrd-phy"; 659 reg = <0x12100000 0x100>; 660 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>; 661 clock-names = "phy", "ref"; 662 samsung,pmu-syscon = <&pmu_system_controller>; 663 #phy-cells = <1>; 664 }; 665 666 ehci: usb@12110000 { 667 compatible = "samsung,exynos4210-ehci"; 668 reg = <0x12110000 0x100>; 669 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 670 671 clocks = <&clock CLK_USB2>; 672 clock-names = "usbhost"; 673 phys = <&usb2_phy_gen 1>; 674 phy-names = "host"; 675 }; 676 677 ohci: usb@12120000 { 678 compatible = "samsung,exynos4210-ohci"; 679 reg = <0x12120000 0x100>; 680 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 681 682 clocks = <&clock CLK_USB2>; 683 clock-names = "usbhost"; 684 phys = <&usb2_phy_gen 1>; 685 phy-names = "host"; 686 }; 687 688 usb2_phy_gen: phy@12130000 { 689 compatible = "samsung,exynos5250-usb2-phy"; 690 reg = <0x12130000 0x100>; 691 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>; 692 clock-names = "phy", "ref"; 693 #phy-cells = <1>; 694 samsung,sysreg-phandle = <&sysreg_system_controller>; 695 samsung,pmureg-phandle = <&pmu_system_controller>; 696 }; 697 698 pdma0: pdma@121a0000 { 699 compatible = "arm,pl330", "arm,primecell"; 700 reg = <0x121A0000 0x1000>; 701 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&clock CLK_PDMA0>; 703 clock-names = "apb_pclk"; 704 #dma-cells = <1>; 705 #dma-channels = <8>; 706 #dma-requests = <32>; 707 }; 708 709 pdma1: pdma@121b0000 { 710 compatible = "arm,pl330", "arm,primecell"; 711 reg = <0x121B0000 0x1000>; 712 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&clock CLK_PDMA1>; 714 clock-names = "apb_pclk"; 715 #dma-cells = <1>; 716 #dma-channels = <8>; 717 #dma-requests = <32>; 718 }; 719 720 mdma0: mdma@10800000 { 721 compatible = "arm,pl330", "arm,primecell"; 722 reg = <0x10800000 0x1000>; 723 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 724 clocks = <&clock CLK_MDMA0>; 725 clock-names = "apb_pclk"; 726 #dma-cells = <1>; 727 #dma-channels = <8>; 728 #dma-requests = <1>; 729 }; 730 731 mdma1: mdma@11c10000 { 732 compatible = "arm,pl330", "arm,primecell"; 733 reg = <0x11C10000 0x1000>; 734 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 735 clocks = <&clock CLK_MDMA1>; 736 clock-names = "apb_pclk"; 737 #dma-cells = <1>; 738 #dma-channels = <8>; 739 #dma-requests = <1>; 740 }; 741 742 gsc_0: gsc@13e00000 { 743 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; 744 reg = <0x13e00000 0x1000>; 745 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 746 power-domains = <&pd_gsc>; 747 clocks = <&clock CLK_GSCL0>; 748 clock-names = "gscl"; 749 iommus = <&sysmmu_gsc0>; 750 }; 751 752 gsc_1: gsc@13e10000 { 753 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; 754 reg = <0x13e10000 0x1000>; 755 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 756 power-domains = <&pd_gsc>; 757 clocks = <&clock CLK_GSCL1>; 758 clock-names = "gscl"; 759 iommus = <&sysmmu_gsc1>; 760 }; 761 762 gsc_2: gsc@13e20000 { 763 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; 764 reg = <0x13e20000 0x1000>; 765 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 766 power-domains = <&pd_gsc>; 767 clocks = <&clock CLK_GSCL2>; 768 clock-names = "gscl"; 769 iommus = <&sysmmu_gsc2>; 770 }; 771 772 gsc_3: gsc@13e30000 { 773 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; 774 reg = <0x13e30000 0x1000>; 775 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 776 power-domains = <&pd_gsc>; 777 clocks = <&clock CLK_GSCL3>; 778 clock-names = "gscl"; 779 iommus = <&sysmmu_gsc3>; 780 }; 781 782 hdmi: hdmi@14530000 { 783 compatible = "samsung,exynos4212-hdmi"; 784 reg = <0x14530000 0x70000>; 785 power-domains = <&pd_disp1>; 786 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 787 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 788 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, 789 <&clock CLK_MOUT_HDMI>; 790 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", 791 "sclk_hdmiphy", "mout_hdmi"; 792 samsung,syscon-phandle = <&pmu_system_controller>; 793 phy = <&hdmiphy>; 794 #sound-dai-cells = <0>; 795 status = "disabled"; 796 }; 797 798 hdmicec: cec@101b0000 { 799 compatible = "samsung,s5p-cec"; 800 reg = <0x101B0000 0x200>; 801 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 802 clocks = <&clock CLK_HDMI_CEC>; 803 clock-names = "hdmicec"; 804 samsung,syscon-phandle = <&pmu_system_controller>; 805 hdmi-phandle = <&hdmi>; 806 pinctrl-names = "default"; 807 pinctrl-0 = <&hdmi_cec>; 808 status = "disabled"; 809 }; 810 811 mixer: mixer@14450000 { 812 compatible = "samsung,exynos5250-mixer"; 813 reg = <0x14450000 0x10000>; 814 power-domains = <&pd_disp1>; 815 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 816 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 817 <&clock CLK_SCLK_HDMI>; 818 clock-names = "mixer", "hdmi", "sclk_hdmi"; 819 iommus = <&sysmmu_tv>; 820 status = "disabled"; 821 }; 822 823 dp_phy: video-phy { 824 compatible = "samsung,exynos5250-dp-video-phy"; 825 samsung,pmu-syscon = <&pmu_system_controller>; 826 #phy-cells = <0>; 827 }; 828 829 mipi_phy: video-phy@10040710 { 830 compatible = "samsung,s5pv210-mipi-video-phy"; 831 reg = <0x10040710 0x100>; 832 #phy-cells = <1>; 833 syscon = <&pmu_system_controller>; 834 }; 835 836 dsi_0: dsi@14500000 { 837 compatible = "samsung,exynos4210-mipi-dsi"; 838 reg = <0x14500000 0x10000>; 839 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 840 samsung,power-domain = <&pd_disp1>; 841 phys = <&mipi_phy 3>; 842 phy-names = "dsim"; 843 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI1>; 844 clock-names = "bus_clk", "sclk_mipi"; 845 status = "disabled"; 846 #address-cells = <1>; 847 #size-cells = <0>; 848 }; 849 850 adc: adc@12d10000 { 851 compatible = "samsung,exynos-adc-v1"; 852 reg = <0x12D10000 0x100>; 853 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&clock CLK_ADC>; 855 clock-names = "adc"; 856 #io-channel-cells = <1>; 857 samsung,syscon-phandle = <&pmu_system_controller>; 858 status = "disabled"; 859 }; 860 861 sysmmu_g2d: sysmmu@10a60000 { 862 compatible = "samsung,exynos-sysmmu"; 863 reg = <0x10A60000 0x1000>; 864 interrupt-parent = <&combiner>; 865 interrupts = <24 5>; 866 clock-names = "sysmmu", "master"; 867 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>; 868 #iommu-cells = <0>; 869 }; 870 871 sysmmu_mfc_r: sysmmu@11200000 { 872 compatible = "samsung,exynos-sysmmu"; 873 reg = <0x11200000 0x1000>; 874 interrupt-parent = <&combiner>; 875 interrupts = <6 2>; 876 power-domains = <&pd_mfc>; 877 clock-names = "sysmmu", "master"; 878 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; 879 #iommu-cells = <0>; 880 }; 881 882 sysmmu_mfc_l: sysmmu@11210000 { 883 compatible = "samsung,exynos-sysmmu"; 884 reg = <0x11210000 0x1000>; 885 interrupt-parent = <&combiner>; 886 interrupts = <8 5>; 887 power-domains = <&pd_mfc>; 888 clock-names = "sysmmu", "master"; 889 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; 890 #iommu-cells = <0>; 891 }; 892 893 sysmmu_rotator: sysmmu@11d40000 { 894 compatible = "samsung,exynos-sysmmu"; 895 reg = <0x11D40000 0x1000>; 896 interrupt-parent = <&combiner>; 897 interrupts = <4 0>; 898 clock-names = "sysmmu", "master"; 899 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; 900 #iommu-cells = <0>; 901 }; 902 903 sysmmu_jpeg: sysmmu@11f20000 { 904 compatible = "samsung,exynos-sysmmu"; 905 reg = <0x11F20000 0x1000>; 906 interrupt-parent = <&combiner>; 907 interrupts = <4 2>; 908 power-domains = <&pd_gsc>; 909 clock-names = "sysmmu", "master"; 910 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; 911 #iommu-cells = <0>; 912 }; 913 914 sysmmu_fimc_isp: sysmmu@13260000 { 915 compatible = "samsung,exynos-sysmmu"; 916 reg = <0x13260000 0x1000>; 917 interrupt-parent = <&combiner>; 918 interrupts = <10 6>; 919 clock-names = "sysmmu"; 920 clocks = <&clock CLK_SMMU_FIMC_ISP>; 921 #iommu-cells = <0>; 922 }; 923 924 sysmmu_fimc_drc: sysmmu@13270000 { 925 compatible = "samsung,exynos-sysmmu"; 926 reg = <0x13270000 0x1000>; 927 interrupt-parent = <&combiner>; 928 interrupts = <11 6>; 929 clock-names = "sysmmu"; 930 clocks = <&clock CLK_SMMU_FIMC_DRC>; 931 #iommu-cells = <0>; 932 }; 933 934 sysmmu_fimc_fd: sysmmu@132a0000 { 935 compatible = "samsung,exynos-sysmmu"; 936 reg = <0x132A0000 0x1000>; 937 interrupt-parent = <&combiner>; 938 interrupts = <5 0>; 939 clock-names = "sysmmu"; 940 clocks = <&clock CLK_SMMU_FIMC_FD>; 941 #iommu-cells = <0>; 942 }; 943 944 sysmmu_fimc_scc: sysmmu@13280000 { 945 compatible = "samsung,exynos-sysmmu"; 946 reg = <0x13280000 0x1000>; 947 interrupt-parent = <&combiner>; 948 interrupts = <5 2>; 949 clock-names = "sysmmu"; 950 clocks = <&clock CLK_SMMU_FIMC_SCC>; 951 #iommu-cells = <0>; 952 }; 953 954 sysmmu_fimc_scp: sysmmu@13290000 { 955 compatible = "samsung,exynos-sysmmu"; 956 reg = <0x13290000 0x1000>; 957 interrupt-parent = <&combiner>; 958 interrupts = <3 6>; 959 clock-names = "sysmmu"; 960 clocks = <&clock CLK_SMMU_FIMC_SCP>; 961 #iommu-cells = <0>; 962 }; 963 964 sysmmu_fimc_mcuctl: sysmmu@132b0000 { 965 compatible = "samsung,exynos-sysmmu"; 966 reg = <0x132B0000 0x1000>; 967 interrupt-parent = <&combiner>; 968 interrupts = <5 4>; 969 clock-names = "sysmmu"; 970 clocks = <&clock CLK_SMMU_FIMC_MCU>; 971 #iommu-cells = <0>; 972 }; 973 974 sysmmu_fimc_odc: sysmmu@132c0000 { 975 compatible = "samsung,exynos-sysmmu"; 976 reg = <0x132C0000 0x1000>; 977 interrupt-parent = <&combiner>; 978 interrupts = <11 0>; 979 clock-names = "sysmmu"; 980 clocks = <&clock CLK_SMMU_FIMC_ODC>; 981 #iommu-cells = <0>; 982 }; 983 984 sysmmu_fimc_dis0: sysmmu@132d0000 { 985 compatible = "samsung,exynos-sysmmu"; 986 reg = <0x132D0000 0x1000>; 987 interrupt-parent = <&combiner>; 988 interrupts = <10 4>; 989 clock-names = "sysmmu"; 990 clocks = <&clock CLK_SMMU_FIMC_DIS0>; 991 #iommu-cells = <0>; 992 }; 993 994 sysmmu_fimc_dis1: sysmmu@132e0000 { 995 compatible = "samsung,exynos-sysmmu"; 996 reg = <0x132E0000 0x1000>; 997 interrupt-parent = <&combiner>; 998 interrupts = <9 4>; 999 clock-names = "sysmmu"; 1000 clocks = <&clock CLK_SMMU_FIMC_DIS1>; 1001 #iommu-cells = <0>; 1002 }; 1003 1004 sysmmu_fimc_3dnr: sysmmu@132f0000 { 1005 compatible = "samsung,exynos-sysmmu"; 1006 reg = <0x132F0000 0x1000>; 1007 interrupt-parent = <&combiner>; 1008 interrupts = <5 6>; 1009 clock-names = "sysmmu"; 1010 clocks = <&clock CLK_SMMU_FIMC_3DNR>; 1011 #iommu-cells = <0>; 1012 }; 1013 1014 sysmmu_fimc_lite0: sysmmu@13c40000 { 1015 compatible = "samsung,exynos-sysmmu"; 1016 reg = <0x13C40000 0x1000>; 1017 interrupt-parent = <&combiner>; 1018 interrupts = <3 4>; 1019 power-domains = <&pd_gsc>; 1020 clock-names = "sysmmu", "master"; 1021 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>; 1022 #iommu-cells = <0>; 1023 }; 1024 1025 sysmmu_fimc_lite1: sysmmu@13c50000 { 1026 compatible = "samsung,exynos-sysmmu"; 1027 reg = <0x13C50000 0x1000>; 1028 interrupt-parent = <&combiner>; 1029 interrupts = <24 1>; 1030 power-domains = <&pd_gsc>; 1031 clock-names = "sysmmu", "master"; 1032 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>; 1033 #iommu-cells = <0>; 1034 }; 1035 1036 sysmmu_gsc0: sysmmu@13e80000 { 1037 compatible = "samsung,exynos-sysmmu"; 1038 reg = <0x13E80000 0x1000>; 1039 interrupt-parent = <&combiner>; 1040 interrupts = <2 0>; 1041 power-domains = <&pd_gsc>; 1042 clock-names = "sysmmu", "master"; 1043 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; 1044 #iommu-cells = <0>; 1045 }; 1046 1047 sysmmu_gsc1: sysmmu@13e90000 { 1048 compatible = "samsung,exynos-sysmmu"; 1049 reg = <0x13E90000 0x1000>; 1050 interrupt-parent = <&combiner>; 1051 interrupts = <2 2>; 1052 power-domains = <&pd_gsc>; 1053 clock-names = "sysmmu", "master"; 1054 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; 1055 #iommu-cells = <0>; 1056 }; 1057 1058 sysmmu_gsc2: sysmmu@13ea0000 { 1059 compatible = "samsung,exynos-sysmmu"; 1060 reg = <0x13EA0000 0x1000>; 1061 interrupt-parent = <&combiner>; 1062 interrupts = <2 4>; 1063 power-domains = <&pd_gsc>; 1064 clock-names = "sysmmu", "master"; 1065 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>; 1066 #iommu-cells = <0>; 1067 }; 1068 1069 sysmmu_gsc3: sysmmu@13eb0000 { 1070 compatible = "samsung,exynos-sysmmu"; 1071 reg = <0x13EB0000 0x1000>; 1072 interrupt-parent = <&combiner>; 1073 interrupts = <2 6>; 1074 power-domains = <&pd_gsc>; 1075 clock-names = "sysmmu", "master"; 1076 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>; 1077 #iommu-cells = <0>; 1078 }; 1079 1080 sysmmu_fimd1: sysmmu@14640000 { 1081 compatible = "samsung,exynos-sysmmu"; 1082 reg = <0x14640000 0x1000>; 1083 interrupt-parent = <&combiner>; 1084 interrupts = <3 2>; 1085 power-domains = <&pd_disp1>; 1086 clock-names = "sysmmu", "master"; 1087 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; 1088 #iommu-cells = <0>; 1089 }; 1090 1091 sysmmu_tv: sysmmu@14650000 { 1092 compatible = "samsung,exynos-sysmmu"; 1093 reg = <0x14650000 0x1000>; 1094 interrupt-parent = <&combiner>; 1095 interrupts = <7 4>; 1096 power-domains = <&pd_disp1>; 1097 clock-names = "sysmmu", "master"; 1098 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; 1099 #iommu-cells = <0>; 1100 }; 1101 }; 1102 1103 timer { 1104 compatible = "arm,armv7-timer"; 1105 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1106 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1107 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1108 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1109 /* 1110 * Unfortunately we need this since some versions 1111 * of U-Boot on Exynos don't set the CNTFRQ register, 1112 * so we need the value from DT. 1113 */ 1114 clock-frequency = <24000000>; 1115 }; 1116}; 1117 1118&cpu_thermal { 1119 polling-delay-passive = <0>; 1120 polling-delay = <0>; 1121 thermal-sensors = <&tmu 0>; 1122 1123 cooling-maps { 1124 map0 { 1125 /* Corresponds to 800MHz at freq_table */ 1126 cooling-device = <&cpu0 9 9>, <&cpu1 9 9>; 1127 }; 1128 map1 { 1129 /* Corresponds to 200MHz at freq_table */ 1130 cooling-device = <&cpu0 15 15>, 1131 <&cpu1 15 15>; 1132 }; 1133 }; 1134}; 1135 1136&dp { 1137 power-domains = <&pd_disp1>; 1138 clocks = <&clock CLK_DP>; 1139 clock-names = "dp"; 1140 phys = <&dp_phy>; 1141 phy-names = "dp"; 1142}; 1143 1144&fimd { 1145 power-domains = <&pd_disp1>; 1146 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; 1147 clock-names = "sclk_fimd", "fimd"; 1148 iommus = <&sysmmu_fimd1>; 1149}; 1150 1151&g2d { 1152 iommus = <&sysmmu_g2d>; 1153 clocks = <&clock CLK_G2D>; 1154 clock-names = "fimg2d"; 1155 status = "okay"; 1156}; 1157 1158&i2c_0 { 1159 clocks = <&clock CLK_I2C0>; 1160 clock-names = "i2c"; 1161 pinctrl-names = "default"; 1162 pinctrl-0 = <&i2c0_bus>; 1163}; 1164 1165&i2c_1 { 1166 clocks = <&clock CLK_I2C1>; 1167 clock-names = "i2c"; 1168 pinctrl-names = "default"; 1169 pinctrl-0 = <&i2c1_bus>; 1170}; 1171 1172&i2c_2 { 1173 clocks = <&clock CLK_I2C2>; 1174 clock-names = "i2c"; 1175 pinctrl-names = "default"; 1176 pinctrl-0 = <&i2c2_bus>; 1177}; 1178 1179&i2c_3 { 1180 clocks = <&clock CLK_I2C3>; 1181 clock-names = "i2c"; 1182 pinctrl-names = "default"; 1183 pinctrl-0 = <&i2c3_bus>; 1184}; 1185 1186&prng { 1187 clocks = <&clock CLK_SSS>; 1188 clock-names = "secss"; 1189}; 1190 1191&pwm { 1192 clocks = <&clock CLK_PWM>; 1193 clock-names = "timers"; 1194}; 1195 1196&rtc { 1197 clocks = <&clock CLK_RTC>; 1198 clock-names = "rtc"; 1199 interrupt-parent = <&pmu_system_controller>; 1200 status = "disabled"; 1201}; 1202 1203&serial_0 { 1204 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 1205 clock-names = "uart", "clk_uart_baud0"; 1206 dmas = <&pdma0 13>, <&pdma0 14>; 1207 dma-names = "rx", "tx"; 1208}; 1209 1210&serial_1 { 1211 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 1212 clock-names = "uart", "clk_uart_baud0"; 1213 dmas = <&pdma1 15>, <&pdma1 16>; 1214 dma-names = "rx", "tx"; 1215}; 1216 1217&serial_2 { 1218 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 1219 clock-names = "uart", "clk_uart_baud0"; 1220 dmas = <&pdma0 15>, <&pdma0 16>; 1221 dma-names = "rx", "tx"; 1222}; 1223 1224&serial_3 { 1225 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; 1226 clock-names = "uart", "clk_uart_baud0"; 1227 dmas = <&pdma1 17>, <&pdma1 18>; 1228 dma-names = "rx", "tx"; 1229}; 1230 1231&sss { 1232 clocks = <&clock CLK_SSS>; 1233 clock-names = "secss"; 1234}; 1235 1236&trng { 1237 clocks = <&clock CLK_SSS>; 1238 clock-names = "secss"; 1239}; 1240 1241#include "exynos5250-pinctrl.dtsi" 1242#include "exynos-syscon-restart.dtsi" 1243