1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
4 */
5
6#include <dt-bindings/clock/hi3519-clock.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8/ {
9	#address-cells = <1>;
10	#size-cells = <1>;
11	chosen { };
12
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu@0 {
18			device_type = "cpu";
19			compatible = "arm,cortex-a7";
20			reg = <0>;
21		};
22	};
23
24	gic: interrupt-controller@10300000 {
25		compatible = "arm,cortex-a7-gic";
26		#interrupt-cells = <3>;
27		interrupt-controller;
28		reg = <0x10301000 0x1000>, <0x10302000 0x1000>;
29	};
30
31	clk_3m: clk_3m {
32		compatible = "fixed-clock";
33		#clock-cells = <0>;
34		clock-frequency = <3000000>;
35	};
36
37	crg: clock-reset-controller@12010000 {
38		compatible = "hisilicon,hi3519-crg";
39		#clock-cells = <1>;
40		#reset-cells = <2>;
41		reg = <0x12010000 0x10000>;
42	};
43
44	soc {
45		#address-cells = <1>;
46		#size-cells = <1>;
47		compatible = "simple-bus";
48		interrupt-parent = <&gic>;
49		ranges;
50
51		uart0: serial@12100000 {
52			compatible = "arm,pl011", "arm,primecell";
53			reg = <0x12100000 0x1000>;
54			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
55			clocks = <&crg HI3519_UART0_CLK>, <&crg HI3519_UART0_CLK>;
56			clock-names = "uartclk", "apb_pclk";
57			status = "disable";
58		};
59
60		uart1: serial@12101000 {
61			compatible = "arm,pl011", "arm,primecell";
62			reg = <0x12101000 0x1000>;
63			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
64			clocks = <&crg HI3519_UART1_CLK>, <&crg HI3519_UART1_CLK>;
65			clock-names = "uartclk", "apb_pclk";
66			status = "disable";
67		};
68
69		uart2: serial@12102000 {
70			compatible = "arm,pl011", "arm,primecell";
71			reg = <0x12102000 0x1000>;
72			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
73			clocks = <&crg HI3519_UART2_CLK>, <&crg HI3519_UART2_CLK>;
74			clock-names = "uartclk", "apb_pclk";
75			status = "disable";
76		};
77
78		uart3: serial@12103000 {
79			compatible = "arm,pl011", "arm,primecell";
80			reg = <0x12103000 0x1000>;
81			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
82			clocks = <&crg HI3519_UART3_CLK>, <&crg HI3519_UART3_CLK>;
83			clock-names = "uartclk", "apb_pclk";
84			status = "disable";
85		};
86
87		uart4: serial@12104000 {
88			compatible = "arm,pl011", "arm,primecell";
89			reg = <0x12104000 0x1000>;
90			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
91			clocks = <&crg HI3519_UART4_CLK>, <&crg HI3519_UART4_CLK>;
92			clock-names = "uartclk", "apb_pclk";
93			status = "disable";
94		};
95
96		dual_timer0: timer@12000000 {
97			compatible = "arm,sp804", "arm,primecell";
98			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
99				     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
100			reg = <0x12000000 0x1000>;
101			clocks = <&clk_3m>;
102			clock-names = "apb_pclk";
103			status = "disable";
104		};
105
106		dual_timer1: timer@12001000 {
107			compatible = "arm,sp804", "arm,primecell";
108			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
109				     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
110			reg = <0x12001000 0x1000>;
111			clocks = <&clk_3m>;
112			clock-names = "apb_pclk";
113			status = "disable";
114		};
115
116		dual_timer2: timer@12002000 {
117			compatible = "arm,sp804", "arm,primecell";
118			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
119				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
120			reg = <0x12002000 0x1000>;
121			clocks = <&clk_3m>;
122			clock-names = "apb_pclk";
123			status = "disable";
124		};
125
126		spi_bus0: spi@12120000 {
127			compatible = "arm,pl022", "arm,primecell";
128			reg = <0x12120000 0x1000>;
129			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
130			clocks = <&crg HI3519_SPI0_CLK>, <&crg HI3519_SPI0_CLK>;
131			clock-names = "sspclk", "apb_pclk";
132			num-cs = <1>;
133			#address-cells = <1>;
134			#size-cells = <0>;
135			status = "disable";
136		};
137
138		spi_bus1: spi@12121000 {
139			compatible = "arm,pl022", "arm,primecell";
140			reg = <0x12121000 0x1000>;
141			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
142			clocks = <&crg HI3519_SPI1_CLK>, <&crg HI3519_SPI1_CLK>;
143			clock-names = "sspclk", "apb_pclk";
144			num-cs = <1>;
145			#address-cells = <1>;
146			#size-cells = <0>;
147			status = "disable";
148		};
149
150		spi_bus2: spi@12122000 {
151			compatible = "arm,pl022", "arm,primecell";
152			reg = <0x12122000 0x1000>;
153			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
154			clocks = <&crg HI3519_SPI2_CLK>, <&crg HI3519_SPI2_CLK>;
155			clock-names = "sspclk", "apb_pclk";
156			num-cs = <1>;
157			#address-cells = <1>;
158			#size-cells = <0>;
159			status = "disable";
160		};
161
162		sysctrl: system-controller@12020000 {
163			compatible = "hisilicon,hi3519-sysctrl", "syscon";
164			reg = <0x12020000 0x1000>;
165		};
166
167		reboot {
168			compatible = "syscon-reboot";
169			regmap = <&sysctrl>;
170			offset = <0x4>;
171			mask = <0xdeadbeef>;
172		};
173	};
174};
175