1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright 2014 Iain Paton <ipaton0@gmail.com>
4 */
5
6/dts-v1/;
7#include "imx6dl.dtsi"
8#include <dt-bindings/gpio/gpio.h>
9
10/ {
11	model = "RIoTboard i.MX6S";
12	compatible = "riot,imx6s-riotboard", "fsl,imx6dl";
13
14	memory@10000000 {
15		device_type = "memory";
16		reg = <0x10000000 0x40000000>;
17	};
18
19	chosen {
20		stdout-path = "serial1:115200n8";
21	};
22
23	leds {
24		compatible = "gpio-leds";
25		pinctrl-names = "default";
26		pinctrl-0 = <&pinctrl_led>;
27
28		led0: user1 {
29			label = "user1";
30			gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
31			default-state = "on";
32			linux,default-trigger = "heartbeat";
33		};
34
35		led1: user2 {
36			label = "user2";
37			gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
38			default-state = "off";
39		};
40	};
41
42	sound {
43		compatible = "fsl,imx-audio-sgtl5000";
44		model = "imx6-riotboard-sgtl5000";
45		ssi-controller = <&ssi1>;
46		audio-codec = <&codec>;
47		audio-routing =
48			"MIC_IN", "Mic Jack",
49			"Mic Jack", "Mic Bias",
50			"Headphone Jack", "HP_OUT";
51			mux-int-port = <1>;
52			mux-ext-port = <3>;
53	};
54
55	reg_2p5v: regulator-2p5v {
56		compatible = "regulator-fixed";
57		regulator-name = "2P5V";
58		regulator-min-microvolt = <2500000>;
59		regulator-max-microvolt = <2500000>;
60	};
61
62	reg_3p3v: regulator-3p3v {
63		compatible = "regulator-fixed";
64		regulator-name = "3P3V";
65		regulator-min-microvolt = <3300000>;
66		regulator-max-microvolt = <3300000>;
67	};
68
69	reg_usb_otg_vbus: regulator-usbotgvbus {
70		compatible = "regulator-fixed";
71		regulator-name = "usb_otg_vbus";
72		regulator-min-microvolt = <5000000>;
73		regulator-max-microvolt = <5000000>;
74		gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
75	};
76};
77
78&audmux {
79	pinctrl-names = "default";
80	pinctrl-0 = <&pinctrl_audmux>;
81	status = "okay";
82};
83
84&clks {
85	fsl,pmic-stby-poweroff;
86};
87
88&fec {
89	pinctrl-names = "default";
90	pinctrl-0 = <&pinctrl_enet>;
91	phy-mode = "rgmii-id";
92	phy-handle = <&rgmii_phy>;
93	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
94			      <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
95	fsl,err006687-workaround-present;
96	status = "okay";
97
98	mdio {
99		#address-cells = <1>;
100		#size-cells = <0>;
101
102		/* Atheros AR8035 PHY */
103		rgmii_phy: ethernet-phy@4 {
104			reg = <4>;
105			interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
106			reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
107			reset-assert-us = <10000>;
108			reset-deassert-us = <1000>;
109			qca,smarteee-tw-us-1g = <24>;
110			qca,clk-out-frequency = <125000000>;
111		};
112	};
113};
114
115&gpio1 {
116	gpio-line-names =
117		"", "", "SD2_WP", "", "SD2_CD", "I2C3_SCL",
118			"I2C3_SDA", "I2C4_SCL",
119		"I2C4_SDA", "", "", "", "", "", "", "",
120		"", "PWM3", "", "", "", "", "", "",
121		"", "", "", "", "", "", "", "";
122};
123
124&gpio3 {
125	gpio-line-names =
126		"", "", "", "", "", "", "", "",
127		"", "", "", "", "", "", "", "",
128		"", "", "", "", "", "", "USB_OTG_VBUS", "",
129		"UART3_TXD", "UART3_RXD", "", "", "EIM_D28", "", "", "";
130};
131
132&gpio4 {
133	gpio-line-names =
134		"", "", "", "", "", "", "UART4_TXD", "UART4_RXD",
135		"UART5_TXD", "UART5_RXD", "", "", "", "", "", "",
136		"GPIO4_16", "GPIO4_17", "GPIO4_18", "GPIO4_19", "",
137			"CSPI3_CLK", "CSPI3_MOSI", "CSPI3_MISO",
138		"CSPI3_CS0", "CSPI3_CS1", "GPIO4_26", "GPIO4_27",
139			"CSPI3_RDY", "PWM1", "PWM2", "GPIO4_31";
140};
141
142&gpio5 {
143	gpio-line-names =
144		"", "", "EIM_A25", "", "", "GPIO5_05", "GPIO5_06",
145			"GPIO5_07",
146		"GPIO5_08", "CSPI2_CS1", "CSPI2_MOSI", "CSPI2_MISO",
147			"CSPI2_CS0", "CSPI2_CLK", "", "",
148		"", "", "", "", "", "", "", "",
149		"", "", "", "", "", "", "", "";
150};
151
152&gpio7 {
153	gpio-line-names =
154		"SD3_CD", "SD3_WP", "", "", "", "", "", "",
155		"", "", "", "", "", "", "", "",
156		"", "", "", "", "", "", "", "",
157		"", "", "", "", "", "", "", "";
158};
159
160&hdmi {
161	ddc-i2c-bus = <&i2c2>;
162	status = "okay";
163};
164
165&i2c1 {
166	clock-frequency = <100000>;
167	pinctrl-names = "default";
168	pinctrl-0 = <&pinctrl_i2c1>;
169	status = "okay";
170
171	codec: sgtl5000@a {
172		compatible = "fsl,sgtl5000";
173		reg = <0x0a>;
174		clocks = <&clks IMX6QDL_CLK_CKO>;
175		VDDA-supply = <&reg_2p5v>;
176		VDDIO-supply = <&reg_3p3v>;
177	};
178
179	pmic: pf0100@8 {
180		compatible = "fsl,pfuze100";
181		reg = <0x08>;
182		interrupt-parent = <&gpio5>;
183		interrupts = <16 8>;
184		fsl,pmic-stby-poweroff;
185
186		regulators {
187			reg_vddcore: sw1ab {				/* VDDARM_IN */
188				regulator-min-microvolt = <300000>;
189				regulator-max-microvolt = <1875000>;
190				regulator-always-on;
191			};
192
193			reg_vddsoc: sw1c {				/* VDDSOC_IN */
194				regulator-min-microvolt = <300000>;
195				regulator-max-microvolt = <1875000>;
196				regulator-always-on;
197			};
198
199			reg_gen_3v3: sw2 {				/* VDDHIGH_IN */
200				regulator-min-microvolt = <800000>;
201				regulator-max-microvolt = <3300000>;
202				regulator-always-on;
203			};
204
205			reg_ddr_1v5a: sw3a {				/* NVCC_DRAM, NVCC_RGMII */
206				regulator-min-microvolt = <400000>;
207				regulator-max-microvolt = <1975000>;
208				regulator-always-on;
209			};
210
211			reg_ddr_1v5b: sw3b {				/* NVCC_DRAM, NVCC_RGMII */
212				regulator-min-microvolt = <400000>;
213				regulator-max-microvolt = <1975000>;
214				regulator-always-on;
215			};
216
217			reg_ddr_vtt: sw4 {				/* MIPI conn */
218				regulator-min-microvolt = <400000>;
219				regulator-max-microvolt = <1975000>;
220				regulator-always-on;
221			};
222
223			reg_5v_600mA: swbst {				/* not used */
224				regulator-min-microvolt = <5000000>;
225				regulator-max-microvolt = <5150000>;
226			};
227
228			reg_snvs_3v: vsnvs {				/* VDD_SNVS_IN */
229				regulator-min-microvolt = <1500000>;
230				regulator-max-microvolt = <3000000>;
231				regulator-always-on;
232			};
233
234			vref_reg: vrefddr {				/* VREF_DDR */
235				regulator-boot-on;
236				regulator-always-on;
237			};
238
239			reg_vgen1_1v5: vgen1 {				/* not used */
240				regulator-min-microvolt = <800000>;
241				regulator-max-microvolt = <1550000>;
242			};
243
244			reg_vgen2_1v2_eth: vgen2 {			/* pcie ? */
245				regulator-min-microvolt = <800000>;
246				regulator-max-microvolt = <1550000>;
247				regulator-always-on;
248			};
249
250			reg_vgen3_2v8: vgen3 {				/* not used */
251				regulator-min-microvolt = <1800000>;
252				regulator-max-microvolt = <3300000>;
253			};
254			reg_vgen4_1v8: vgen4 {				/* NVCC_SD3 */
255				regulator-min-microvolt = <1800000>;
256				regulator-max-microvolt = <3300000>;
257				regulator-always-on;
258			};
259
260			reg_vgen5_2v5_sgtl: vgen5 {			/* Pwr LED & 5V0_delayed enable */
261				regulator-min-microvolt = <1800000>;
262				regulator-max-microvolt = <3300000>;
263				regulator-always-on;
264			};
265
266			reg_vgen6_3v3: vgen6 {				/* #V#_DELAYED enable, MIPI */
267				regulator-min-microvolt = <1800000>;
268				regulator-max-microvolt = <3300000>;
269				regulator-always-on;
270			};
271		};
272	};
273};
274
275&i2c2 {
276	clock-frequency = <100000>;
277	pinctrl-names = "default";
278	pinctrl-0 = <&pinctrl_i2c2>;
279	status = "okay";
280};
281
282&i2c4 {
283	clock-frequency = <100000>;
284	pinctrl-names = "default";
285	pinctrl-0 = <&pinctrl_i2c4>;
286	clocks = <&clks 116>;
287	status = "okay";
288};
289
290&pwm1 {
291	pinctrl-names = "default";
292	pinctrl-0 = <&pinctrl_pwm1>;
293	status = "okay";
294};
295
296&pwm2 {
297	pinctrl-names = "default";
298	pinctrl-0 = <&pinctrl_pwm2>;
299	status = "okay";
300};
301
302&pwm3 {
303	pinctrl-names = "default";
304	pinctrl-0 = <&pinctrl_pwm3>;
305	status = "okay";
306};
307
308&pwm4 {
309	pinctrl-names = "default";
310	pinctrl-0 = <&pinctrl_pwm4>;
311	status = "okay";
312};
313
314&ssi1 {
315	status = "okay";
316};
317
318&uart1 {
319	pinctrl-names = "default";
320	pinctrl-0 = <&pinctrl_uart1>;
321	status = "okay";
322};
323
324&uart2 {
325	pinctrl-names = "default";
326	pinctrl-0 = <&pinctrl_uart2>;
327	status = "okay";
328};
329
330&uart3 {
331	pinctrl-names = "default";
332	pinctrl-0 = <&pinctrl_uart3>;
333	status = "okay";
334};
335
336&uart4 {
337	pinctrl-names = "default";
338	pinctrl-0 = <&pinctrl_uart4>;
339	status = "okay";
340};
341
342&uart5 {
343	pinctrl-names = "default";
344	pinctrl-0 = <&pinctrl_uart5>;
345	status = "okay";
346};
347
348&usbh1 {
349	dr_mode = "host";
350	disable-over-current;
351	status = "okay";
352};
353
354&usbotg {
355	vbus-supply = <&reg_usb_otg_vbus>;
356	pinctrl-names = "default";
357	pinctrl-0 = <&pinctrl_usbotg>;
358	disable-over-current;
359	dr_mode = "otg";
360	status = "okay";
361};
362
363&usdhc2 {
364	pinctrl-names = "default";
365	pinctrl-0 = <&pinctrl_usdhc2>;
366	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
367	wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
368	vmmc-supply = <&reg_3p3v>;
369	status = "okay";
370};
371
372&usdhc3 {
373	pinctrl-names = "default";
374	pinctrl-0 = <&pinctrl_usdhc3>;
375	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
376	wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
377	vmmc-supply = <&reg_3p3v>;
378	status = "okay";
379};
380
381&usdhc4 {
382	pinctrl-names = "default";
383	pinctrl-0 = <&pinctrl_usdhc4>;
384	vmmc-supply = <&reg_3p3v>;
385	non-removable;
386	status = "okay";
387};
388
389&iomuxc {
390	pinctrl-names = "default";
391
392	imx6-riotboard {
393		pinctrl_audmux: audmuxgrp {
394			fsl,pins = <
395				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
396				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
397				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
398				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
399				MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0		/* CAM_MCLK */
400			>;
401		};
402
403		pinctrl_ecspi1: ecspi1grp {
404			fsl,pins = <
405				MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
406				MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
407				MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
408				MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17	0x000b1		/* CS0 */
409			>;
410		};
411
412		pinctrl_ecspi2: ecspi2grp {
413			fsl,pins = <
414				MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09	0x000b1		/* CS1 */
415				MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI	0x100b1
416				MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO	0x100b1
417				MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12	0x000b1		/* CS0 */
418				MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK	0x100b1
419			>;
420		};
421
422		pinctrl_ecspi3: ecspi3grp {
423			fsl,pins = <
424				MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK	0x100b1
425				MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI	0x100b1
426				MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO	0x100b1
427				MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24	0x000b1		/* CS0 */
428				MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25	0x000b1		/* CS1 */
429			>;
430		};
431
432		pinctrl_enet: enetgrp {
433			fsl,pins = <
434				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
435				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
436				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
437				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
438				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
439				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
440				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
441				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
442				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x0a0b1		/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
443				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030		/* AR8035 pin strapping: IO voltage: pull up */
444				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x13030		/* AR8035 pin strapping: PHYADDR#0: pull down */
445				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x13030		/* AR8035 pin strapping: PHYADDR#1: pull down */
446				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030		/* AR8035 pin strapping: MODE#1: pull up */
447				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030		/* AR8035 pin strapping: MODE#3: pull up */
448				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x130b0		/* AR8035 pin strapping: MODE#0: pull down */
449				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8	/* GPIO16 -> AR8035 25MHz */
450				MX6QDL_PAD_EIM_D31__GPIO3_IO31		0x130b0		/* RGMII_nRST */
451				MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x180b0		/* AR8035 interrupt */
452				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
453			>;
454		};
455
456		pinctrl_i2c1: i2c1grp {
457			fsl,pins = <
458				MX6QDL_PAD_CSI0_DAT8__I2C1_SDA		0x4001b8b1
459				MX6QDL_PAD_CSI0_DAT9__I2C1_SCL		0x4001b8b1
460			>;
461		};
462
463		pinctrl_i2c2: i2c2grp {
464			fsl,pins = <
465				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
466				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
467			>;
468		};
469
470		pinctrl_i2c3: i2c3grp {
471			fsl,pins = <
472				MX6QDL_PAD_GPIO_5__I2C3_SCL		0x4001b8b1
473				MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
474			>;
475		};
476
477		pinctrl_i2c4: i2c4grp {
478			fsl,pins = <
479				MX6QDL_PAD_GPIO_7__I2C4_SCL             0x4001b8b1
480				MX6QDL_PAD_GPIO_8__I2C4_SDA             0x4001b8b1
481			>;
482		};
483
484		pinctrl_led: ledgrp {
485			fsl,pins = <
486				MX6QDL_PAD_EIM_A25__GPIO5_IO02		0x1b0b1	/* user led0 */
487				MX6QDL_PAD_EIM_D28__GPIO3_IO28		0x1b0b1	/* user led1 */
488			>;
489		};
490
491		pinctrl_pwm1: pwm1grp {
492			fsl,pins = <
493				MX6QDL_PAD_DISP0_DAT8__PWM1_OUT		0x1b0b1
494			>;
495		};
496
497		pinctrl_pwm2: pwm2grp {
498			fsl,pins = <
499				MX6QDL_PAD_DISP0_DAT9__PWM2_OUT		0x1b0b1
500			>;
501		};
502
503		pinctrl_pwm3: pwm3grp {
504			fsl,pins = <
505				MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
506			>;
507		};
508
509		pinctrl_pwm4: pwm4grp {
510			fsl,pins = <
511				MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
512			>;
513		};
514
515		pinctrl_uart1: uart1grp {
516			fsl,pins = <
517				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
518				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
519			>;
520		};
521
522		pinctrl_uart2: uart2grp {
523			fsl,pins = <
524				MX6QDL_PAD_EIM_D26__UART2_TX_DATA	0x1b0b1
525				MX6QDL_PAD_EIM_D27__UART2_RX_DATA	0x1b0b1
526			>;
527		};
528
529		pinctrl_uart3: uart3grp {
530			fsl,pins = <
531				MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
532				MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
533			>;
534		};
535
536		pinctrl_uart4: uart4grp {
537			fsl,pins = <
538				MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1
539				MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1
540			>;
541		};
542
543		pinctrl_uart5: uart5grp {
544			fsl,pins = <
545				MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
546				MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
547			>;
548		};
549
550		pinctrl_usbotg: usbotggrp {
551			fsl,pins = <
552				MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x17059
553				MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x000b0	/* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */
554				MX6QDL_PAD_EIM_D21__USB_OTG_OC		0x1b0b0
555			>;
556		};
557
558		pinctrl_usdhc2: usdhc2grp {
559			fsl,pins = <
560				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
561				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
562				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
563				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
564				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
565				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
566				MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x1b0b0	/* SD2 CD */
567				MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x1f0b0	/* SD2 WP */
568			>;
569		};
570
571		pinctrl_usdhc3: usdhc3grp {
572			fsl,pins = <
573				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
574				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
575				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
576				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
577				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
578				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
579				MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x1b0b0	/* SD3 CD */
580				MX6QDL_PAD_SD3_DAT4__GPIO7_IO01		0x1f0b0	/* SD3 WP */
581			>;
582		};
583
584		pinctrl_usdhc4: usdhc4grp {
585			fsl,pins = <
586				MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
587				MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
588				MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
589				MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
590				MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
591				MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
592				MX6QDL_PAD_NANDF_ALE__GPIO6_IO08	0x17059	/* SD4 RST (eMMC) */
593			>;
594		};
595	};
596};
597