1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/ {
11	/* these are used by bootloader for disabling nodes */
12	aliases {
13		led0 = &led0;
14		led1 = &led1;
15		led2 = &led2;
16		nand = &gpmi;
17		ssi0 = &ssi1;
18		usb0 = &usbh1;
19		usb1 = &usbotg;
20	};
21
22	chosen {
23		bootargs = "console=ttymxc1,115200";
24	};
25
26	backlight {
27		compatible = "pwm-backlight";
28		pwms = <&pwm4 0 5000000>;
29		brightness-levels = <0 4 8 16 32 64 128 255>;
30		default-brightness-level = <7>;
31	};
32
33	gpio-keys {
34		compatible = "gpio-keys";
35
36		user-pb {
37			label = "user_pb";
38			gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
39			linux,code = <BTN_0>;
40		};
41
42		user-pb1x {
43			label = "user_pb1x";
44			linux,code = <BTN_1>;
45			interrupt-parent = <&gsc>;
46			interrupts = <0>;
47		};
48
49		key-erased {
50			label = "key-erased";
51			linux,code = <BTN_2>;
52			interrupt-parent = <&gsc>;
53			interrupts = <1>;
54		};
55
56		eeprom-wp {
57			label = "eeprom_wp";
58			linux,code = <BTN_3>;
59			interrupt-parent = <&gsc>;
60			interrupts = <2>;
61		};
62
63		tamper {
64			label = "tamper";
65			linux,code = <BTN_4>;
66			interrupt-parent = <&gsc>;
67			interrupts = <5>;
68		};
69
70		switch-hold {
71			label = "switch_hold";
72			linux,code = <BTN_5>;
73			interrupt-parent = <&gsc>;
74			interrupts = <7>;
75		};
76	};
77
78	leds {
79		compatible = "gpio-leds";
80		pinctrl-names = "default";
81		pinctrl-0 = <&pinctrl_gpio_leds>;
82
83		led0: user1 {
84			label = "user1";
85			gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
86			default-state = "on";
87			linux,default-trigger = "heartbeat";
88		};
89
90		led1: user2 {
91			label = "user2";
92			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
93			default-state = "off";
94		};
95
96		led2: user3 {
97			label = "user3";
98			gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
99			default-state = "off";
100		};
101	};
102
103	memory@10000000 {
104		device_type = "memory";
105		reg = <0x10000000 0x20000000>;
106	};
107
108	pps {
109		compatible = "pps-gpio";
110		pinctrl-names = "default";
111		pinctrl-0 = <&pinctrl_pps>;
112		gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
113		status = "okay";
114	};
115
116	reg_1p0v: regulator-1p0v {
117		compatible = "regulator-fixed";
118		regulator-name = "1P0V";
119		regulator-min-microvolt = <1000000>;
120		regulator-max-microvolt = <1000000>;
121		regulator-always-on;
122	};
123
124	reg_3p3v: regulator-3p3v {
125		compatible = "regulator-fixed";
126		regulator-name = "3P3V";
127		regulator-min-microvolt = <3300000>;
128		regulator-max-microvolt = <3300000>;
129		regulator-always-on;
130	};
131
132	reg_5p0v: regulator-5p0v {
133		compatible = "regulator-fixed";
134		regulator-name = "5P0V";
135		regulator-min-microvolt = <5000000>;
136		regulator-max-microvolt = <5000000>;
137		regulator-always-on;
138	};
139
140	reg_usb_otg_vbus: regulator-usb-otg-vbus {
141		compatible = "regulator-fixed";
142		regulator-name = "usb_otg_vbus";
143		regulator-min-microvolt = <5000000>;
144		regulator-max-microvolt = <5000000>;
145		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
146		enable-active-high;
147	};
148
149	sound {
150		compatible = "fsl,imx6q-ventana-sgtl5000",
151			     "fsl,imx-audio-sgtl5000";
152		model = "sgtl5000-audio";
153		ssi-controller = <&ssi1>;
154		audio-codec = <&codec>;
155		audio-routing =
156			"MIC_IN", "Mic Jack",
157			"Mic Jack", "Mic Bias",
158			"Headphone Jack", "HP_OUT";
159		mux-int-port = <1>;
160		mux-ext-port = <4>;
161	};
162};
163
164&audmux {
165	pinctrl-names = "default";
166	pinctrl-0 = <&pinctrl_audmux>;
167	status = "okay";
168};
169
170&can1 {
171	pinctrl-names = "default";
172	pinctrl-0 = <&pinctrl_flexcan1>;
173	status = "okay";
174};
175
176&clks {
177	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
178			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
179	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
180				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
181};
182
183&ecspi3 {
184	cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
185	pinctrl-names = "default";
186	pinctrl-0 = <&pinctrl_ecspi3>;
187	status = "okay";
188};
189
190&fec {
191	pinctrl-names = "default";
192	pinctrl-0 = <&pinctrl_enet>;
193	phy-mode = "rgmii-id";
194	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
195	status = "okay";
196};
197
198&gpmi {
199	pinctrl-names = "default";
200	pinctrl-0 = <&pinctrl_gpmi_nand>;
201	status = "okay";
202};
203
204&hdmi {
205	ddc-i2c-bus = <&i2c3>;
206	status = "okay";
207};
208
209&i2c1 {
210	clock-frequency = <100000>;
211	pinctrl-names = "default";
212	pinctrl-0 = <&pinctrl_i2c1>;
213	status = "okay";
214
215	gsc: gsc@20 {
216		compatible = "gw,gsc";
217		reg = <0x20>;
218		interrupt-parent = <&gpio1>;
219		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
220		interrupt-controller;
221		#interrupt-cells = <1>;
222		#size-cells = <0>;
223
224		adc {
225			compatible = "gw,gsc-adc";
226			#address-cells = <1>;
227			#size-cells = <0>;
228
229			channel@0 {
230				gw,mode = <0>;
231				reg = <0x00>;
232				label = "temp";
233			};
234
235			channel@2 {
236				gw,mode = <1>;
237				reg = <0x02>;
238				label = "vdd_vin";
239			};
240
241			channel@5 {
242				gw,mode = <1>;
243				reg = <0x05>;
244				label = "vdd_3p3";
245			};
246
247			channel@8 {
248				gw,mode = <1>;
249				reg = <0x08>;
250				label = "vdd_bat";
251			};
252
253			channel@b {
254				gw,mode = <1>;
255				reg = <0x0b>;
256				label = "vdd_5p0";
257			};
258
259			channel@e {
260				gw,mode = <1>;
261				reg = <0xe>;
262				label = "vdd_arm";
263			};
264
265			channel@11 {
266				gw,mode = <1>;
267				reg = <0x11>;
268				label = "vdd_soc";
269			};
270
271			channel@14 {
272				gw,mode = <1>;
273				reg = <0x14>;
274				label = "vdd_3p0";
275			};
276
277			channel@17 {
278				gw,mode = <1>;
279				reg = <0x17>;
280				label = "vdd_1p5";
281			};
282
283			channel@1d {
284				gw,mode = <1>;
285				reg = <0x1d>;
286				label = "vdd_1p8";
287			};
288
289			channel@20 {
290				gw,mode = <1>;
291				reg = <0x20>;
292				label = "vdd_1p0";
293			};
294
295			channel@23 {
296				gw,mode = <1>;
297				reg = <0x23>;
298				label = "vdd_2p5";
299			};
300
301			channel@29 {
302				gw,mode = <1>;
303				reg = <0x29>;
304				label = "vdd_an1";
305			};
306		};
307	};
308
309	gsc_gpio: gpio@23 {
310		compatible = "nxp,pca9555";
311		reg = <0x23>;
312		gpio-controller;
313		#gpio-cells = <2>;
314		interrupt-parent = <&gsc>;
315		interrupts = <4>;
316	};
317
318	eeprom1: eeprom@50 {
319		compatible = "atmel,24c02";
320		reg = <0x50>;
321		pagesize = <16>;
322	};
323
324	eeprom2: eeprom@51 {
325		compatible = "atmel,24c02";
326		reg = <0x51>;
327		pagesize = <16>;
328	};
329
330	eeprom3: eeprom@52 {
331		compatible = "atmel,24c02";
332		reg = <0x52>;
333		pagesize = <16>;
334	};
335
336	eeprom4: eeprom@53 {
337		compatible = "atmel,24c02";
338		reg = <0x53>;
339		pagesize = <16>;
340	};
341
342	rtc: ds1672@68 {
343		compatible = "dallas,ds1672";
344		reg = <0x68>;
345	};
346};
347
348&i2c2 {
349	clock-frequency = <100000>;
350	pinctrl-names = "default";
351	pinctrl-0 = <&pinctrl_i2c2>;
352	status = "okay";
353
354	ltc3676: pmic@3c {
355		compatible = "lltc,ltc3676";
356		reg = <0x3c>;
357		pinctrl-names = "default";
358		pinctrl-0 = <&pinctrl_pmic>;
359		interrupt-parent = <&gpio1>;
360		interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
361
362		regulators {
363			/* VDD_SOC (1+R1/R2 = 1.635) */
364			reg_vdd_soc: sw1 {
365				regulator-name = "vddsoc";
366				regulator-min-microvolt = <674400>;
367				regulator-max-microvolt = <1308000>;
368				lltc,fb-voltage-divider = <127000 200000>;
369				regulator-ramp-delay = <7000>;
370				regulator-boot-on;
371				regulator-always-on;
372			};
373
374			/* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
375			reg_1p8v: sw2 {
376				regulator-name = "vdd1p8";
377				regulator-min-microvolt = <1033310>;
378				regulator-max-microvolt = <2004000>;
379				lltc,fb-voltage-divider = <301000 200000>;
380				regulator-ramp-delay = <7000>;
381				regulator-boot-on;
382				regulator-always-on;
383			};
384
385			/* VDD_ARM (1+R1/R2 = 1.635) */
386			reg_vdd_arm: sw3 {
387				regulator-name = "vddarm";
388				regulator-min-microvolt = <674400>;
389				regulator-max-microvolt = <1308000>;
390				lltc,fb-voltage-divider = <127000 200000>;
391				regulator-ramp-delay = <7000>;
392				regulator-boot-on;
393				regulator-always-on;
394			};
395
396			/* VDD_DDR (1+R1/R2 = 2.105) */
397			reg_vdd_ddr: sw4 {
398				regulator-name = "vddddr";
399				regulator-min-microvolt = <868310>;
400				regulator-max-microvolt = <1684000>;
401				lltc,fb-voltage-divider = <221000 200000>;
402				regulator-ramp-delay = <7000>;
403				regulator-boot-on;
404				regulator-always-on;
405			};
406
407			/* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
408			reg_2p5v: ldo2 {
409				regulator-name = "vdd2p5";
410				regulator-min-microvolt = <2490375>;
411				regulator-max-microvolt = <2490375>;
412				lltc,fb-voltage-divider = <487000 200000>;
413				regulator-boot-on;
414				regulator-always-on;
415			};
416
417			/* VDD_AUD_1P8: Audio codec */
418			reg_aud_1p8v: ldo3 {
419				regulator-name = "vdd1p8a";
420				regulator-min-microvolt = <1800000>;
421				regulator-max-microvolt = <1800000>;
422				regulator-boot-on;
423			};
424
425			/* VDD_HIGH (1+R1/R2 = 4.17) */
426			reg_3p0v: ldo4 {
427				regulator-name = "vdd3p0";
428				regulator-min-microvolt = <3023250>;
429				regulator-max-microvolt = <3023250>;
430				lltc,fb-voltage-divider = <634000 200000>;
431				regulator-boot-on;
432				regulator-always-on;
433			};
434		};
435	};
436};
437
438&i2c3 {
439	clock-frequency = <100000>;
440	pinctrl-names = "default";
441	pinctrl-0 = <&pinctrl_i2c3>;
442	status = "okay";
443
444	codec: sgtl5000@a {
445		compatible = "fsl,sgtl5000";
446		reg = <0x0a>;
447		clocks = <&clks IMX6QDL_CLK_CKO>;
448		VDDA-supply = <&reg_1p8v>;
449		VDDIO-supply = <&reg_3p3v>;
450	};
451
452	touchscreen: egalax_ts@4 {
453		compatible = "eeti,egalax_ts";
454		reg = <0x04>;
455		interrupt-parent = <&gpio7>;
456		interrupts = <12 2>;
457		wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
458	};
459
460	accel@1e {
461		compatible = "nxp,fxos8700";
462		reg = <0x1e>;
463	};
464};
465
466&ldb {
467	status = "okay";
468
469	lvds-channel@0 {
470		fsl,data-mapping = "spwg";
471		fsl,data-width = <18>;
472		status = "okay";
473
474		display-timings {
475			native-mode = <&timing0>;
476			timing0: hsd100pxn1 {
477				clock-frequency = <65000000>;
478				hactive = <1024>;
479				vactive = <768>;
480				hback-porch = <220>;
481				hfront-porch = <40>;
482				vback-porch = <21>;
483				vfront-porch = <7>;
484				hsync-len = <60>;
485				vsync-len = <10>;
486			};
487		};
488	};
489};
490
491&pcie {
492	pinctrl-names = "default";
493	pinctrl-0 = <&pinctrl_pcie>;
494	reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
495	status = "okay";
496};
497
498&pwm2 {
499	pinctrl-names = "default";
500	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
501	status = "disabled";
502};
503
504&pwm3 {
505	pinctrl-names = "default";
506	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
507	status = "disabled";
508};
509
510&pwm4 {
511	#pwm-cells = <2>;
512	pinctrl-names = "default";
513	pinctrl-0 = <&pinctrl_pwm4>;
514	status = "okay";
515};
516
517&ssi1 {
518	status = "okay";
519};
520
521&uart1 {
522	pinctrl-names = "default";
523	pinctrl-0 = <&pinctrl_uart1>;
524	rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
525	status = "okay";
526};
527
528&uart2 {
529	pinctrl-names = "default";
530	pinctrl-0 = <&pinctrl_uart2>;
531	status = "okay";
532};
533
534&uart5 {
535	pinctrl-names = "default";
536	pinctrl-0 = <&pinctrl_uart5>;
537	status = "okay";
538};
539
540&usbotg {
541	vbus-supply = <&reg_usb_otg_vbus>;
542	pinctrl-names = "default";
543	pinctrl-0 = <&pinctrl_usbotg>;
544	disable-over-current;
545	status = "okay";
546};
547
548&usbh1 {
549	status = "okay";
550};
551
552&usdhc3 {
553	pinctrl-names = "default", "state_100mhz", "state_200mhz";
554	pinctrl-0 = <&pinctrl_usdhc3>;
555	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
556	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
557	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
558	vmmc-supply = <&reg_3p3v>;
559	no-1-8-v; /* firmware will remove if board revision supports */
560	status = "okay";
561};
562
563&wdog1 {
564	pinctrl-names = "default";
565	pinctrl-0 = <&pinctrl_wdog>;
566	fsl,ext-reset-output;
567};
568
569&iomuxc {
570	pinctrl_audmux: audmuxgrp {
571		fsl,pins = <
572			MX6QDL_PAD_SD2_DAT0__AUD4_RXD		0x130b0
573			MX6QDL_PAD_SD2_DAT3__AUD4_TXC		0x130b0
574			MX6QDL_PAD_SD2_DAT2__AUD4_TXD		0x110b0
575			MX6QDL_PAD_SD2_DAT1__AUD4_TXFS		0x130b0
576			MX6QDL_PAD_GPIO_0__CCM_CLKO1	0x130b0 /* AUD4_MCK */
577		>;
578	};
579
580	pinctrl_ecspi3: escpi3grp {
581		fsl,pins = <
582			MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK	0x100b1
583			MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI	0x100b1
584			MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO	0x100b1
585			MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24	0x100b1
586		>;
587	};
588
589	pinctrl_enet: enetgrp {
590		fsl,pins = <
591			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
592			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
593			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
594			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
595			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
596			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
597			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
598			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
599			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
600			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
601			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
602			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
603			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
604			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
605			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
606			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
607			MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x1b0b0 /* PHY Reset */
608		>;
609	};
610
611	pinctrl_flexcan1: flexcan1grp {
612		fsl,pins = <
613			MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX	0x1b0b1
614			MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b1
615			MX6QDL_PAD_GPIO_9__GPIO1_IO09		0x4001b0b0 /* CAN_STBY */
616		>;
617	};
618
619	pinctrl_gpio_leds: gpioledsgrp {
620		fsl,pins = <
621			MX6QDL_PAD_KEY_COL0__GPIO4_IO06  0x1b0b0
622			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07  0x1b0b0
623			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15  0x1b0b0
624		>;
625	};
626
627	pinctrl_gpmi_nand: gpminandgrp {
628		fsl,pins = <
629			MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
630			MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
631			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
632			MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
633			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
634			MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
635			MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
636			MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
637			MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
638			MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
639			MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
640			MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
641			MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
642			MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
643			MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
644		>;
645	};
646
647	pinctrl_i2c1: i2c1grp {
648		fsl,pins = <
649			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
650			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
651			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0xb0b1
652		>;
653	};
654
655	pinctrl_i2c2: i2c2grp {
656		fsl,pins = <
657			MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
658			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
659		>;
660	};
661
662	pinctrl_i2c3: i2c3grp {
663		fsl,pins = <
664			MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
665			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
666		>;
667	};
668
669	pinctrl_pcie: pciegrp {
670		fsl,pins = <
671			MX6QDL_PAD_ENET_TXD1__GPIO1_IO29	0x1b0b0 /* PCIE_RST# */
672		>;
673	};
674
675	pinctrl_pmic: pmicgrp {
676		fsl,pins = <
677			MX6QDL_PAD_GPIO_8__GPIO1_IO08		0x0001b0b0 /* PMIC_IRQ# */
678		>;
679	};
680
681	pinctrl_pps: ppsgrp {
682		fsl,pins = <
683			MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x1b0b1
684		>;
685	};
686
687	pinctrl_pwm2: pwm2grp {
688		fsl,pins = <
689			MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
690		>;
691	};
692
693	pinctrl_pwm3: pwm3grp {
694		fsl,pins = <
695			MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
696		>;
697	};
698
699	pinctrl_pwm4: pwm4grp {
700		fsl,pins = <
701			MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
702		>;
703	};
704
705	pinctrl_uart1: uart1grp {
706		fsl,pins = <
707			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
708			MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
709			MX6QDL_PAD_SD3_DAT4__GPIO7_IO01		0x4001b0b1 /* TEN */
710		>;
711	};
712
713	pinctrl_uart2: uart2grp {
714		fsl,pins = <
715			MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
716			MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
717		>;
718	};
719
720	pinctrl_uart5: uart5grp {
721		fsl,pins = <
722			MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
723			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
724		>;
725	};
726
727	pinctrl_usbotg: usbotggrp {
728		fsl,pins = <
729			MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
730			MX6QDL_PAD_EIM_D22__GPIO3_IO22	0x1b0b0 /* OTG_PWR_EN */
731			MX6QDL_PAD_KEY_COL4__USB_OTG_OC		0x17059
732		>;
733	};
734
735	pinctrl_usdhc3: usdhc3grp {
736		fsl,pins = <
737			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
738			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
739			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
740			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
741			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
742			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
743			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x17059 /* CD */
744			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x17059
745		>;
746	};
747
748	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
749		fsl,pins = <
750			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170b9
751			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x170b9
752			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
753			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
754			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
755			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
756			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170b9 /* CD */
757			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170b9
758		>;
759	};
760
761	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
762		fsl,pins = <
763			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170f9
764			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100f9
765			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
766			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
767			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
768			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
769			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170f9 /* CD */
770			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170f9
771		>;
772	};
773
774	pinctrl_wdog: wdoggrp {
775		fsl,pins = <
776			MX6QDL_PAD_DISP0_DAT8__WDOG1_B		0x1b0b0
777		>;
778	};
779};
780