1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/sound/fsl-imx-audmux.h>
10
11/ {
12	/* these are used by bootloader for disabling nodes */
13	aliases {
14		led0 = &led0;
15		led1 = &led1;
16		led2 = &led2;
17		nand = &gpmi;
18		ssi0 = &ssi1;
19		usb0 = &usbh1;
20		usb1 = &usbotg;
21	};
22
23	chosen {
24		bootargs = "console=ttymxc1,115200";
25	};
26
27	backlight {
28		compatible = "pwm-backlight";
29		pwms = <&pwm4 0 5000000>;
30		brightness-levels = <0 4 8 16 32 64 128 255>;
31		default-brightness-level = <7>;
32	};
33
34	gpio-keys {
35		compatible = "gpio-keys";
36
37		user-pb {
38			label = "user_pb";
39			gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
40			linux,code = <BTN_0>;
41		};
42
43		user-pb1x {
44			label = "user_pb1x";
45			linux,code = <BTN_1>;
46			interrupt-parent = <&gsc>;
47			interrupts = <0>;
48		};
49
50		key-erased {
51			label = "key-erased";
52			linux,code = <BTN_2>;
53			interrupt-parent = <&gsc>;
54			interrupts = <1>;
55		};
56
57		eeprom-wp {
58			label = "eeprom_wp";
59			linux,code = <BTN_3>;
60			interrupt-parent = <&gsc>;
61			interrupts = <2>;
62		};
63
64		tamper {
65			label = "tamper";
66			linux,code = <BTN_4>;
67			interrupt-parent = <&gsc>;
68			interrupts = <5>;
69		};
70
71		switch-hold {
72			label = "switch_hold";
73			linux,code = <BTN_5>;
74			interrupt-parent = <&gsc>;
75			interrupts = <7>;
76		};
77	};
78
79	leds {
80		compatible = "gpio-leds";
81		pinctrl-names = "default";
82		pinctrl-0 = <&pinctrl_gpio_leds>;
83
84		led0: user1 {
85			label = "user1";
86			gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
87			default-state = "on";
88			linux,default-trigger = "heartbeat";
89		};
90
91		led1: user2 {
92			label = "user2";
93			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
94			default-state = "off";
95		};
96
97		led2: user3 {
98			label = "user3";
99			gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
100			default-state = "off";
101		};
102	};
103
104	memory@10000000 {
105		device_type = "memory";
106		reg = <0x10000000 0x40000000>;
107	};
108
109	pps {
110		compatible = "pps-gpio";
111		pinctrl-names = "default";
112		pinctrl-0 = <&pinctrl_pps>;
113		gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
114		status = "okay";
115	};
116
117	regulators {
118		compatible = "simple-bus";
119		#address-cells = <1>;
120		#size-cells = <0>;
121
122		reg_1p0v: regulator@0 {
123			compatible = "regulator-fixed";
124			reg = <0>;
125			regulator-name = "1P0V";
126			regulator-min-microvolt = <1000000>;
127			regulator-max-microvolt = <1000000>;
128			regulator-always-on;
129		};
130
131		reg_3p3v: regulator@1 {
132			compatible = "regulator-fixed";
133			reg = <1>;
134			regulator-name = "3P3V";
135			regulator-min-microvolt = <3300000>;
136			regulator-max-microvolt = <3300000>;
137			regulator-always-on;
138		};
139
140		reg_usb_h1_vbus: regulator@2 {
141			compatible = "regulator-fixed";
142			reg = <2>;
143			regulator-name = "usb_h1_vbus";
144			regulator-min-microvolt = <5000000>;
145			regulator-max-microvolt = <5000000>;
146			regulator-always-on;
147		};
148
149		reg_usb_otg_vbus: regulator@3 {
150			compatible = "regulator-fixed";
151			reg = <3>;
152			regulator-name = "usb_otg_vbus";
153			regulator-min-microvolt = <5000000>;
154			regulator-max-microvolt = <5000000>;
155			gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
156			enable-active-high;
157		};
158	};
159
160	sound-analog {
161		compatible = "fsl,imx6q-ventana-sgtl5000",
162			     "fsl,imx-audio-sgtl5000";
163		model = "sgtl5000-audio";
164		ssi-controller = <&ssi1>;
165		audio-codec = <&sgtl5000>;
166		audio-routing =
167			"MIC_IN", "Mic Jack",
168			"Mic Jack", "Mic Bias",
169			"Headphone Jack", "HP_OUT";
170		mux-int-port = <1>;
171		mux-ext-port = <4>;
172	};
173};
174
175&audmux {
176	pinctrl-names = "default";
177	pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
178	status = "okay";
179
180	ssi2 {
181		fsl,audmux-port = <1>;
182		fsl,port-config = <
183			(IMX_AUDMUX_V2_PTCR_TFSDIR |
184			IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
185			IMX_AUDMUX_V2_PTCR_TCLKDIR |
186			IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
187			IMX_AUDMUX_V2_PTCR_SYN)
188			IMX_AUDMUX_V2_PDCR_RXDSEL(4)
189		>;
190	};
191
192	aud5 {
193		fsl,audmux-port = <4>;
194		fsl,port-config = <
195			IMX_AUDMUX_V2_PTCR_SYN
196			IMX_AUDMUX_V2_PDCR_RXDSEL(1)>;
197	};
198};
199
200&can1 {
201	pinctrl-names = "default";
202	pinctrl-0 = <&pinctrl_flexcan1>;
203	status = "okay";
204};
205
206&clks {
207	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
208			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
209	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
210				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
211};
212
213&ecspi2 {
214	cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
215	pinctrl-names = "default";
216	pinctrl-0 = <&pinctrl_ecspi2>;
217	status = "okay";
218};
219
220&fec {
221	pinctrl-names = "default";
222	pinctrl-0 = <&pinctrl_enet>;
223	phy-mode = "rgmii-id";
224	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
225	status = "okay";
226};
227
228&gpmi {
229	pinctrl-names = "default";
230	pinctrl-0 = <&pinctrl_gpmi_nand>;
231	status = "okay";
232};
233
234&hdmi {
235	ddc-i2c-bus = <&i2c3>;
236	status = "okay";
237};
238
239&i2c1 {
240	clock-frequency = <100000>;
241	pinctrl-names = "default";
242	pinctrl-0 = <&pinctrl_i2c1>;
243	status = "okay";
244
245	gsc: gsc@20 {
246		compatible = "gw,gsc";
247		reg = <0x20>;
248		interrupt-parent = <&gpio1>;
249		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
250		interrupt-controller;
251		#interrupt-cells = <1>;
252		#address-cells = <1>;
253		#size-cells = <0>;
254
255		adc {
256			compatible = "gw,gsc-adc";
257			#address-cells = <1>;
258			#size-cells = <0>;
259
260			channel@0 {
261				gw,mode = <0>;
262				reg = <0x00>;
263				label = "temp";
264			};
265
266			channel@2 {
267				gw,mode = <1>;
268				reg = <0x02>;
269				label = "vdd_vin";
270			};
271
272			channel@5 {
273				gw,mode = <1>;
274				reg = <0x05>;
275				label = "vdd_3p3";
276			};
277
278			channel@8 {
279				gw,mode = <1>;
280				reg = <0x08>;
281				label = "vdd_bat";
282			};
283
284			channel@b {
285				gw,mode = <1>;
286				reg = <0x0b>;
287				label = "vdd_5p0";
288			};
289
290			channel@e {
291				gw,mode = <1>;
292				reg = <0xe>;
293				label = "vdd_arm";
294			};
295
296			channel@11 {
297				gw,mode = <1>;
298				reg = <0x11>;
299				label = "vdd_soc";
300			};
301
302			channel@14 {
303				gw,mode = <1>;
304				reg = <0x14>;
305				label = "vdd_3p0";
306			};
307
308			channel@17 {
309				gw,mode = <1>;
310				reg = <0x17>;
311				label = "vdd_1p5";
312			};
313
314			channel@1d {
315				gw,mode = <1>;
316				reg = <0x1d>;
317				label = "vdd_1p8";
318			};
319
320			channel@20 {
321				gw,mode = <1>;
322				reg = <0x20>;
323				label = "vdd_1p0";
324			};
325
326			channel@23 {
327				gw,mode = <1>;
328				reg = <0x23>;
329				label = "vdd_2p5";
330			};
331
332			channel@26 {
333				gw,mode = <1>;
334				reg = <0x26>;
335				label = "vdd_gps";
336			};
337		};
338
339		fan-controller@2c {
340			compatible = "gw,gsc-fan";
341			#address-cells = <1>;
342			#size-cells = <0>;
343			reg = <0x2c>;
344		};
345	};
346
347	gsc_gpio: gpio@23 {
348		compatible = "nxp,pca9555";
349		reg = <0x23>;
350		gpio-controller;
351		#gpio-cells = <2>;
352		interrupt-parent = <&gsc>;
353		interrupts = <4>;
354	};
355
356	eeprom1: eeprom@50 {
357		compatible = "atmel,24c02";
358		reg = <0x50>;
359		pagesize = <16>;
360	};
361
362	eeprom2: eeprom@51 {
363		compatible = "atmel,24c02";
364		reg = <0x51>;
365		pagesize = <16>;
366	};
367
368	eeprom3: eeprom@52 {
369		compatible = "atmel,24c02";
370		reg = <0x52>;
371		pagesize = <16>;
372	};
373
374	eeprom4: eeprom@53 {
375		compatible = "atmel,24c02";
376		reg = <0x53>;
377		pagesize = <16>;
378	};
379
380	rtc: ds1672@68 {
381		compatible = "dallas,ds1672";
382		reg = <0x68>;
383	};
384};
385
386&i2c2 {
387	clock-frequency = <100000>;
388	pinctrl-names = "default";
389	pinctrl-0 = <&pinctrl_i2c2>;
390	status = "okay";
391
392	pmic: pfuze100@8 {
393		compatible = "fsl,pfuze100";
394		reg = <0x08>;
395
396		regulators {
397			sw1a_reg: sw1ab {
398				regulator-min-microvolt = <300000>;
399				regulator-max-microvolt = <1875000>;
400				regulator-boot-on;
401				regulator-always-on;
402				regulator-ramp-delay = <6250>;
403			};
404
405			sw1c_reg: sw1c {
406				regulator-min-microvolt = <300000>;
407				regulator-max-microvolt = <1875000>;
408				regulator-boot-on;
409				regulator-always-on;
410				regulator-ramp-delay = <6250>;
411			};
412
413			sw2_reg: sw2 {
414				regulator-min-microvolt = <800000>;
415				regulator-max-microvolt = <3950000>;
416				regulator-boot-on;
417				regulator-always-on;
418			};
419
420			sw3a_reg: sw3a {
421				regulator-min-microvolt = <400000>;
422				regulator-max-microvolt = <1975000>;
423				regulator-boot-on;
424				regulator-always-on;
425			};
426
427			sw3b_reg: sw3b {
428				regulator-min-microvolt = <400000>;
429				regulator-max-microvolt = <1975000>;
430				regulator-boot-on;
431				regulator-always-on;
432			};
433
434			sw4_reg: sw4 {
435				regulator-min-microvolt = <800000>;
436				regulator-max-microvolt = <3300000>;
437			};
438
439			swbst_reg: swbst {
440				regulator-min-microvolt = <5000000>;
441				regulator-max-microvolt = <5150000>;
442				regulator-boot-on;
443				regulator-always-on;
444			};
445
446			snvs_reg: vsnvs {
447				regulator-min-microvolt = <1000000>;
448				regulator-max-microvolt = <3000000>;
449				regulator-boot-on;
450				regulator-always-on;
451			};
452
453			vref_reg: vrefddr {
454				regulator-boot-on;
455				regulator-always-on;
456			};
457
458			vgen1_reg: vgen1 {
459				regulator-min-microvolt = <800000>;
460				regulator-max-microvolt = <1550000>;
461			};
462
463			vgen2_reg: vgen2 {
464				regulator-min-microvolt = <800000>;
465				regulator-max-microvolt = <1550000>;
466			};
467
468			vgen3_reg: vgen3 {
469				regulator-min-microvolt = <1800000>;
470				regulator-max-microvolt = <3300000>;
471			};
472
473			vgen4_reg: vgen4 {
474				regulator-min-microvolt = <1800000>;
475				regulator-max-microvolt = <3300000>;
476				regulator-always-on;
477			};
478
479			vgen5_reg: vgen5 {
480				regulator-min-microvolt = <1800000>;
481				regulator-max-microvolt = <3300000>;
482				regulator-always-on;
483			};
484
485			vgen6_reg: vgen6 {
486				regulator-min-microvolt = <1800000>;
487				regulator-max-microvolt = <3300000>;
488				regulator-always-on;
489			};
490		};
491	};
492};
493
494&i2c3 {
495	clock-frequency = <100000>;
496	pinctrl-names = "default";
497	pinctrl-0 = <&pinctrl_i2c3>;
498	status = "okay";
499
500	sgtl5000: audio-codec@a {
501		compatible = "fsl,sgtl5000";
502		reg = <0x0a>;
503		clocks = <&clks IMX6QDL_CLK_CKO>;
504		VDDA-supply = <&sw4_reg>;
505		VDDIO-supply = <&reg_3p3v>;
506	};
507
508	touchscreen: egalax_ts@4 {
509		compatible = "eeti,egalax_ts";
510		reg = <0x04>;
511		interrupt-parent = <&gpio7>;
512		interrupts = <12 2>;
513		wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
514	};
515
516	accel@1e {
517		compatible = "nxp,fxos8700";
518		reg = <0x1e>;
519	};
520};
521
522&ldb {
523	status = "okay";
524
525	lvds-channel@0 {
526		fsl,data-mapping = "spwg";
527		fsl,data-width = <18>;
528		status = "okay";
529
530		display-timings {
531			native-mode = <&timing0>;
532			timing0: hsd100pxn1 {
533				clock-frequency = <65000000>;
534				hactive = <1024>;
535				vactive = <768>;
536				hback-porch = <220>;
537				hfront-porch = <40>;
538				vback-porch = <21>;
539				vfront-porch = <7>;
540				hsync-len = <60>;
541				vsync-len = <10>;
542			};
543		};
544	};
545};
546
547&pcie {
548	pinctrl-names = "default";
549	pinctrl-0 = <&pinctrl_pcie>;
550	reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
551	status = "okay";
552};
553
554&pwm1 {
555	pinctrl-names = "default";
556	pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
557	status = "disabled";
558};
559
560&pwm2 {
561	pinctrl-names = "default";
562	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
563	status = "disabled";
564};
565
566&pwm3 {
567	pinctrl-names = "default";
568	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
569	status = "disabled";
570};
571
572&pwm4 {
573	#pwm-cells = <2>;
574	pinctrl-names = "default", "state_dio";
575	pinctrl-0 = <&pinctrl_pwm4_backlight>;
576	pinctrl-1 = <&pinctrl_pwm4_dio>;
577	status = "okay";
578};
579
580&ssi1 {
581	status = "okay";
582};
583
584&ssi2 {
585	status = "okay";
586};
587
588&uart1 {
589	pinctrl-names = "default";
590	pinctrl-0 = <&pinctrl_uart1>;
591	rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
592	status = "okay";
593};
594
595&uart2 {
596	pinctrl-names = "default";
597	pinctrl-0 = <&pinctrl_uart2>;
598	status = "okay";
599};
600
601&uart5 {
602	pinctrl-names = "default";
603	pinctrl-0 = <&pinctrl_uart5>;
604	status = "okay";
605};
606
607&usbotg {
608	vbus-supply = <&reg_usb_otg_vbus>;
609	pinctrl-names = "default";
610	pinctrl-0 = <&pinctrl_usbotg>;
611	disable-over-current;
612	status = "okay";
613};
614
615&usbh1 {
616	vbus-supply = <&reg_usb_h1_vbus>;
617	status = "okay";
618};
619
620&usdhc3 {
621	pinctrl-names = "default", "state_100mhz", "state_200mhz";
622	pinctrl-0 = <&pinctrl_usdhc3>;
623	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
624	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
625	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
626	vmmc-supply = <&reg_3p3v>;
627	no-1-8-v; /* firmware will remove if board revision supports */
628	status = "okay";
629};
630
631&wdog1 {
632	status = "disabled";
633};
634
635&wdog2 {
636	pinctrl-names = "default";
637	pinctrl-0 = <&pinctrl_wdog>;
638	fsl,ext-reset-output;
639	status = "okay";
640};
641
642&iomuxc {
643	pinctrl_audmux: audmuxgrp {
644		fsl,pins = <
645			MX6QDL_PAD_SD2_DAT0__AUD4_RXD		0x130b0
646			MX6QDL_PAD_SD2_DAT3__AUD4_TXC		0x130b0
647			MX6QDL_PAD_SD2_DAT2__AUD4_TXD		0x110b0
648			MX6QDL_PAD_SD2_DAT1__AUD4_TXFS		0x130b0
649			MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0 /* AUD4_MCK */
650			MX6QDL_PAD_EIM_D25__AUD5_RXC            0x130b0
651			MX6QDL_PAD_DISP0_DAT19__AUD5_RXD        0x130b0
652			MX6QDL_PAD_EIM_D24__AUD5_RXFS           0x130b0
653		>;
654	};
655
656	pinctrl_enet: enetgrp {
657		fsl,pins = <
658			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
659			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
660			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
661			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
662			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
663			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
664			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
665			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
666			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
667			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
668			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
669			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
670			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
671			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
672			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
673			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
674		>;
675	};
676
677	pinctrl_ecspi2: escpi2grp {
678		fsl,pins = <
679			MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK	0x100b1
680			MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI	0x100b1
681			MX6QDL_PAD_EIM_OE__ECSPI2_MISO	0x100b1
682			MX6QDL_PAD_EIM_RW__GPIO2_IO26	0x100b1
683		>;
684	};
685
686	pinctrl_flexcan1: flexcan1grp {
687		fsl,pins = <
688			MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX	0x1b0b1
689			MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b1
690			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x4001b0b0 /* CAN_STBY */
691		>;
692	};
693
694	pinctrl_gpio_leds: gpioledsgrp {
695		fsl,pins = <
696			MX6QDL_PAD_KEY_COL0__GPIO4_IO06		0x1b0b0
697			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07		0x1b0b0
698			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x1b0b0
699		>;
700	};
701
702	pinctrl_gpmi_nand: gpminandgrp {
703		fsl,pins = <
704			MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
705			MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
706			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
707			MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
708			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
709			MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
710			MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
711			MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
712			MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
713			MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
714			MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
715			MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
716			MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
717			MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
718			MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
719		>;
720	};
721
722	pinctrl_i2c1: i2c1grp {
723		fsl,pins = <
724			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
725			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
726			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0xb0b1
727		>;
728	};
729
730	pinctrl_i2c2: i2c2grp {
731		fsl,pins = <
732			MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
733			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
734		>;
735	};
736
737	pinctrl_i2c3: i2c3grp {
738		fsl,pins = <
739			MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
740			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
741		>;
742	};
743
744	pinctrl_pcie: pciegrp {
745		fsl,pins = <
746			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x1b0b0 /* PCIE IRQ */
747			MX6QDL_PAD_ENET_TXD1__GPIO1_IO29	0x1b0b0 /* PCIE RST */
748		>;
749	};
750
751	pinctrl_pps: ppsgrp {
752		fsl,pins = <
753			MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x1b0b1
754		>;
755	};
756
757	pinctrl_pwm1: pwm1grp {
758		fsl,pins = <
759			MX6QDL_PAD_GPIO_9__PWM1_OUT		0x1b0b1
760		>;
761	};
762
763	pinctrl_pwm2: pwm2grp {
764		fsl,pins = <
765			MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
766		>;
767	};
768
769	pinctrl_pwm3: pwm3grp {
770		fsl,pins = <
771			MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
772		>;
773	};
774
775	pinctrl_pwm4_backlight: pwm4grpbacklight {
776		fsl,pins = <
777			/* LVDS_PWM J6.5 */
778			MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
779		>;
780	};
781
782	pinctrl_pwm4_dio: pwm4grpdio {
783		fsl,pins = <
784			/* DIO3 J16.4 */
785			MX6QDL_PAD_SD4_DAT2__PWM4_OUT		0x1b0b1
786		>;
787	};
788
789	pinctrl_uart1: uart1grp {
790		fsl,pins = <
791			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
792			MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
793			MX6QDL_PAD_SD3_DAT4__GPIO7_IO01		0x4001b0b1 /* TEN */
794		>;
795	};
796
797	pinctrl_uart2: uart2grp {
798		fsl,pins = <
799			MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
800			MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
801		>;
802	};
803
804	pinctrl_uart5: uart5grp {
805		fsl,pins = <
806			MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
807			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
808		>;
809	};
810
811	pinctrl_usbotg: usbotggrp {
812		fsl,pins = <
813			MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
814			MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x1b0b0 /* PWR_EN */
815			MX6QDL_PAD_KEY_COL4__USB_OTG_OC		0x17059
816		>;
817	};
818
819	pinctrl_usdhc3: usdhc3grp {
820		fsl,pins = <
821			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
822			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
823			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
824			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
825			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
826			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
827			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x17059 /* CD */
828			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x17059
829		>;
830	};
831
832	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
833		fsl,pins = <
834			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170b9
835			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100b9
836			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
837			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
838			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
839			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
840			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170b9 /* CD */
841			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170b9
842		>;
843	};
844
845	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
846		fsl,pins = <
847			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170f9
848			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100f9
849			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
850			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
851			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
852			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
853			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170f9 /* CD */
854			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170f9
855		>;
856	};
857
858	pinctrl_wdog: wdoggrp {
859		fsl,pins = <
860			MX6QDL_PAD_SD1_DAT3__WDOG2_B		0x1b0b0
861		>;
862	};
863};
864