1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 PHYTEC Messtechnik GmbH
4 * Author: Christian Hemp <c.hemp@phytec.de>
5 */
6
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/regulator/dlg,da9063-regulator.h>
9
10/ {
11	aliases {
12		rtc1 = &da9062_rtc;
13		rtc2 = &snvs_rtc;
14	};
15
16	/*
17	 * Set the minimum memory size here and
18	 * let the bootloader set the real size.
19	 */
20	memory@10000000 {
21		device_type = "memory";
22		reg = <0x10000000 0x8000000>;
23	};
24
25	gpio_leds_som: somleds {
26		compatible = "gpio-leds";
27		pinctrl-names = "default";
28		pinctrl-0 = <&pinctrl_gpioleds_som>;
29
30		som-led-green {
31			label = "phycore:green";
32			gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
33			linux,default-trigger = "heartbeat";
34		};
35	};
36};
37
38&ecspi1 {
39	pinctrl-names = "default";
40	pinctrl-0 = <&pinctrl_ecspi1>;
41	cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
42	status = "okay";
43
44	m25p80: flash@0 {
45		compatible = "jedec,spi-nor";
46		spi-max-frequency = <20000000>;
47		reg = <0>;
48		status = "disabled";
49	};
50};
51
52&fec {
53	pinctrl-names = "default";
54	pinctrl-0 = <&pinctrl_enet>;
55	phy-handle = <&ethphy>;
56	phy-mode = "rgmii";
57	phy-supply = <&vdd_eth_io>;
58	phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
59	status = "disabled";
60
61	mdio {
62		#address-cells = <1>;
63		#size-cells = <0>;
64
65		ethphy: ethernet-phy@3 {
66			reg = <3>;
67			txc-skew-ps = <1680>;
68			rxc-skew-ps = <1860>;
69		};
70	};
71};
72
73&gpmi {
74	pinctrl-names = "default";
75	pinctrl-0 = <&pinctrl_gpmi_nand>;
76	nand-on-flash-bbt;
77	status = "disabled";
78};
79
80&i2c3 {
81	pinctrl-names = "default", "gpio";
82	pinctrl-0 = <&pinctrl_i2c3>;
83	pinctrl-1 = <&pinctrl_i2c3_gpio>;
84	scl-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
85	sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
86	clock-frequency = <400000>;
87	status = "okay";
88
89	eeprom@50 {
90		compatible = "st,24c32", "atmel,24c32";
91		pagesize = <32>;
92		reg = <0x50>;
93	};
94
95	pmic: pmic@58 {
96		compatible = "dlg,da9062";
97		pinctrl-names = "default";
98		pinctrl-0 = <&pinctrl_pmic>;
99		reg = <0x58>;
100		interrupt-parent = <&gpio1>;
101		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
102		interrupt-controller;
103		gpio-controller;
104		#gpio-cells = <2>;
105
106		da9062_rtc: rtc {
107			compatible = "dlg,da9062-rtc";
108		};
109
110		da9062_onkey: onkey {
111			compatible = "dlg,da9062-onkey";
112		};
113
114		watchdog {
115			compatible = "dlg,da9062-watchdog";
116			dlg,use-sw-pm;
117		};
118
119		regulators {
120			vdd_arm: buck1 {
121				regulator-name = "vdd_arm";
122				regulator-min-microvolt = <925000>;
123				regulator-max-microvolt = <1380000>;
124				regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
125				regulator-always-on;
126			};
127
128			vdd_soc: buck2 {
129				regulator-name = "vdd_soc";
130				regulator-min-microvolt = <1150000>;
131				regulator-max-microvolt = <1380000>;
132				regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
133				regulator-always-on;
134			};
135
136			vdd_ddr3_1p5: buck3 {
137				regulator-name = "vdd_ddr3";
138				regulator-min-microvolt = <1500000>;
139				regulator-max-microvolt = <1500000>;
140				regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
141				regulator-always-on;
142			};
143
144			vdd_eth_1p2: buck4 {
145				regulator-name = "vdd_eth";
146				regulator-min-microvolt = <1200000>;
147				regulator-max-microvolt = <1200000>;
148				regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
149				regulator-always-on;
150			};
151
152			vdd_snvs: ldo1 {
153				regulator-name = "vdd_snvs";
154				regulator-min-microvolt = <3000000>;
155				regulator-max-microvolt = <3000000>;
156				regulator-always-on;
157			};
158
159			vdd_high: ldo2 {
160				regulator-name = "vdd_high";
161				regulator-min-microvolt = <3000000>;
162				regulator-max-microvolt = <3000000>;
163				regulator-always-on;
164			};
165
166			vdd_eth_io: ldo3 {
167				regulator-name = "vdd_eth_io";
168				regulator-min-microvolt = <2500000>;
169				regulator-max-microvolt = <2500000>;
170			};
171
172			vdd_emmc_1p8: ldo4 {
173				regulator-name = "vdd_emmc";
174				regulator-min-microvolt = <1800000>;
175				regulator-max-microvolt = <1800000>;
176			};
177		};
178	};
179};
180
181&reg_arm {
182	vin-supply = <&vdd_arm>;
183};
184
185&reg_pu {
186	vin-supply = <&vdd_soc>;
187};
188
189&reg_soc {
190	vin-supply = <&vdd_soc>;
191};
192
193&snvs_poweroff {
194	status = "okay";
195};
196
197&usdhc4 {
198	pinctrl-names = "default";
199	pinctrl-0 = <&pinctrl_usdhc4>;
200	bus-width = <8>;
201	non-removable;
202	status = "disabled";
203};
204
205&iomuxc {
206	pinctrl_enet: enetgrp {
207		fsl,pins = <
208			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
209			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
210			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
211			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
212			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
213			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
214			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
215			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
216			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
217			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
218			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
219			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
220			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
221			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
222			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
223			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
224			MX6QDL_PAD_SD2_DAT1__GPIO1_IO14		0x1b0b0
225		>;
226	};
227
228	pinctrl_gpioleds_som: gpioledssomgrp {
229		fsl,pins = <
230			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x1b0b0
231		>;
232	};
233
234	pinctrl_gpmi_nand: gpminandgrp {
235		fsl,pins = <
236			MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
237			MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
238			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
239			MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
240			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
241			MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
242			MX6QDL_PAD_NANDF_CS2__NAND_CE2_B	0xb0b1
243			MX6QDL_PAD_NANDF_CS3__NAND_CE3_B	0xb0b1
244			MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
245			MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
246			MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
247			MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
248			MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
249			MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
250			MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
251			MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
252			MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
253			MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
254			MX6QDL_PAD_SD4_DAT0__NAND_DQS		0x00b1
255		>;
256	};
257
258	pinctrl_i2c3: i2c3grp {
259		fsl,pins = <
260			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
261			MX6QDL_PAD_GPIO_5__I2C3_SCL		0x4001b8b1
262		>;
263	};
264
265	pinctrl_i2c3_gpio: i2c3gpiogrp {
266		fsl,pins = <
267			MX6QDL_PAD_GPIO_6__GPIO1_IO06	0x4001b8b1
268			MX6QDL_PAD_GPIO_5__GPIO1_IO05	0x4001b8b1
269		>;
270	};
271
272	pinctrl_ecspi1: ecspi1grp {
273		fsl,pins = <
274			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
275			MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
276			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
277			MX6QDL_PAD_EIM_D19__GPIO3_IO19		0x1b0b0
278		>;
279	};
280
281	pinctrl_pmic: pmicgrp {
282		fsl,pins = <
283			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x1b0b0
284		>;
285	};
286
287	pinctrl_usdhc4: usdhc4grp {
288		fsl,pins = <
289			MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
290			MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
291			MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
292			MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
293			MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
294			MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
295			MX6QDL_PAD_SD4_DAT4__SD4_DATA4		0x17059
296			MX6QDL_PAD_SD4_DAT5__SD4_DATA5		0x17059
297			MX6QDL_PAD_SD4_DAT6__SD4_DATA6		0x17059
298			MX6QDL_PAD_SD4_DAT7__SD4_DATA7		0x17059
299		>;
300	};
301};
302