1// SPDX-License-Identifier: GPL-2.0 OR X11
2/*
3 * Copyright (C) 2016 Boundary Devices, Inc.
4 */
5
6/dts-v1/;
7
8#include "imx6sx.dtsi"
9
10/ {
11	model = "Boundary Devices i.MX6 SoloX Nitrogen6sx Board";
12	compatible = "boundary,imx6sx-nitrogen6sx", "fsl,imx6sx";
13
14	memory@80000000 {
15		device_type = "memory";
16		reg = <0x80000000 0x40000000>;
17	};
18
19	backlight-lvds {
20		compatible = "pwm-backlight";
21		pwms = <&pwm4 0 5000000>;
22		brightness-levels = <0 4 8 16 32 64 128 255>;
23		default-brightness-level = <6>;
24		power-supply = <&reg_3p3v>;
25	};
26
27	reg_1p8v: regulator-1p8v {
28		compatible = "regulator-fixed";
29		regulator-name = "1P8V";
30		regulator-min-microvolt = <1800000>;
31		regulator-max-microvolt = <1800000>;
32		regulator-always-on;
33	};
34
35	reg_3p3v: regulator-3p3v {
36		compatible = "regulator-fixed";
37		regulator-name = "3P3V";
38		regulator-min-microvolt = <3300000>;
39		regulator-max-microvolt = <3300000>;
40		regulator-always-on;
41	};
42
43	reg_can1_3v3: regulator-can1-3v3 {
44		compatible = "regulator-fixed";
45		regulator-name = "can1-3v3";
46		regulator-min-microvolt = <3300000>;
47		regulator-max-microvolt = <3300000>;
48		gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
49	};
50
51	reg_can2_3v3: regulator-can2-3v3 {
52		compatible = "regulator-fixed";
53		regulator-name = "can2-3v3";
54		regulator-min-microvolt = <3300000>;
55		regulator-max-microvolt = <3300000>;
56		gpio = <&gpio4 24 GPIO_ACTIVE_LOW>;
57	};
58
59	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
60		pinctrl-names = "default";
61		pinctrl-0 = <&pinctrl_usbotg1_vbus>;
62		compatible = "regulator-fixed";
63		regulator-name = "usb_otg1_vbus";
64		regulator-min-microvolt = <5000000>;
65		regulator-max-microvolt = <5000000>;
66		gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
67		enable-active-high;
68	};
69
70	reg_wlan: regulator-wlan {
71		pinctrl-names = "default";
72		pinctrl-0 = <&pinctrl_reg_wlan>;
73		compatible = "regulator-fixed";
74		clocks = <&clks IMX6SX_CLK_CKO>;
75		clock-names = "slow";
76		regulator-name = "wlan-en";
77		regulator-min-microvolt = <3300000>;
78		regulator-max-microvolt = <3300000>;
79		startup-delay-us = <70000>;
80		gpio = <&gpio7 6 GPIO_ACTIVE_HIGH>;
81		enable-active-high;
82	};
83
84	sound {
85		compatible = "fsl,imx-audio-sgtl5000";
86		model = "imx6sx-nitrogen6sx-sgtl5000";
87		cpu-dai = <&ssi1>;
88		audio-codec = <&codec>;
89		audio-routing =
90			"MIC_IN", "Mic Jack",
91			"Mic Jack", "Mic Bias",
92			"Headphone Jack", "HP_OUT";
93		mux-int-port = <1>;
94		mux-ext-port = <5>;
95	};
96};
97
98&audmux {
99	pinctrl-names = "default";
100	pinctrl-0 = <&pinctrl_audmux>;
101	status = "okay";
102};
103
104&ecspi1 {
105	cs-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>;
106	pinctrl-names = "default";
107	pinctrl-0 = <&pinctrl_ecspi1>;
108	status = "okay";
109
110	flash: m25p80@0 {
111		compatible = "microchip,sst25vf016b";
112		spi-max-frequency = <20000000>;
113		reg = <0>;
114		#address-cells = <1>;
115		#size-cells = <1>;
116
117		partition@0 {
118			label = "U-Boot";
119			reg = <0x0 0xc0000>;
120			read-only;
121		};
122
123		partition@c0000 {
124			label = "env";
125			reg = <0xc0000 0x2000>;
126			read-only;
127		};
128
129		partition@c2000 {
130			label = "Kernel";
131			reg = <0xc2000 0x11e000>;
132		};
133
134		partition@1e0000 {
135			label = "M4";
136			reg = <0x1e0000 0x20000>;
137		};
138	};
139};
140
141&fec1 {
142	pinctrl-names = "default";
143	pinctrl-0 = <&pinctrl_enet1>;
144	phy-mode = "rgmii";
145	phy-handle = <&ethphy1>;
146	phy-supply = <&reg_3p3v>;
147	fsl,magic-packet;
148	status = "okay";
149
150	mdio {
151		#address-cells = <1>;
152		#size-cells = <0>;
153
154		ethphy1: ethernet-phy@4 {
155			reg = <4>;
156		};
157
158		ethphy2: ethernet-phy@5 {
159			reg = <5>;
160		};
161	};
162};
163
164&fec2 {
165	pinctrl-names = "default";
166	pinctrl-0 = <&pinctrl_enet2>;
167	phy-mode = "rgmii";
168	phy-handle = <&ethphy2>;
169	phy-supply = <&reg_3p3v>;
170	fsl,magic-packet;
171	status = "okay";
172};
173
174&flexcan1 {
175	pinctrl-names = "default";
176	pinctrl-0 = <&pinctrl_flexcan1>;
177	xceiver-supply = <&reg_can1_3v3>;
178	status = "okay";
179};
180
181&flexcan2 {
182	pinctrl-names = "default";
183	pinctrl-0 = <&pinctrl_flexcan2>;
184	xceiver-supply = <&reg_can2_3v3>;
185	status = "okay";
186};
187
188&i2c1 {
189	clock-frequency = <100000>;
190	pinctrl-names = "default";
191	pinctrl-0 = <&pinctrl_i2c1>;
192	status = "okay";
193
194	codec: sgtl5000@a {
195		compatible = "fsl,sgtl5000";
196		pinctrl-names = "default";
197		pinctrl-0 = <&pinctrl_sgtl5000>;
198		reg = <0x0a>;
199		clocks = <&clks IMX6SX_CLK_CKO2>;
200		VDDA-supply = <&reg_1p8v>;
201		VDDIO-supply = <&reg_1p8v>;
202		VDDD-supply = <&reg_1p8v>;
203		assigned-clocks = <&clks IMX6SX_CLK_CKO2_SEL>,
204				  <&clks IMX6SX_CLK_CKO2>;
205		assigned-clock-parents = <&clks IMX6SX_CLK_OSC>;
206		assigned-clock-rates = <0>, <24000000>;
207	};
208};
209
210&i2c2 {
211	clock-frequency = <100000>;
212	pinctrl-names = "default";
213	pinctrl-0 = <&pinctrl_i2c2>;
214	status = "okay";
215};
216
217&i2c3 {
218	clock-frequency = <100000>;
219	pinctrl-names = "default";
220	pinctrl-0 = <&pinctrl_i2c3>;
221	status = "okay";
222};
223
224&pcie {
225	pinctrl-names = "default";
226	pinctrl-0 = <&pinctrl_pcie>;
227	reset-gpio = <&gpio4 10 GPIO_ACTIVE_LOW>;
228	status = "okay";
229};
230
231&pwm4 {
232	#pwm-cells = <2>;
233	pinctrl-names = "default";
234	pinctrl-0 = <&pinctrl_pwm4>;
235	status = "okay";
236};
237
238&ssi1 {
239	status = "okay";
240};
241
242&uart1 {
243	pinctrl-names = "default";
244	pinctrl-0 = <&pinctrl_uart1>;
245	status = "okay";
246};
247
248&uart2 {
249	pinctrl-names = "default";
250	pinctrl-0 = <&pinctrl_uart2>;
251	status = "okay";
252};
253
254&uart3 {
255	pinctrl-names = "default";
256	pinctrl-0 = <&pinctrl_uart3>;
257	uart-has-rtscts;
258	status = "okay";
259};
260
261&uart5 {
262	pinctrl-names = "default";
263	pinctrl-0 = <&pinctrl_uart5>;
264	status = "okay";
265};
266
267&usbotg1 {
268	vbus-supply = <&reg_usb_otg1_vbus>;
269	pinctrl-names = "default";
270	pinctrl-0 = <&pinctrl_usbotg1>;
271	status = "okay";
272};
273
274&usbotg2 {
275	pinctrl-names = "default";
276	pinctrl-0 = <&pinctrl_usbotg2>;
277	dr_mode = "host";
278	disable-over-current;
279	reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
280	status = "okay";
281};
282
283&usdhc2 {
284	pinctrl-names = "default";
285	pinctrl-0 = <&pinctrl_usdhc2>;
286	bus-width = <4>;
287	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
288	keep-power-in-suspend;
289	wakeup-source;
290	status = "okay";
291};
292
293&usdhc3 {
294	#address-cells = <1>;
295	#size-cells = <0>;
296	pinctrl-names = "default";
297	pinctrl-0 = <&pinctrl_usdhc3>;
298	bus-width = <4>;
299	non-removable;
300	keep-power-in-suspend;
301	vmmc-supply = <&reg_wlan>;
302	cap-power-off-card;
303	cap-sdio-irq;
304	status = "okay";
305
306	brcmf: wifi@1 {
307		reg = <1>;
308		compatible = "brcm,bcm4329-fmac";
309		interrupt-parent = <&gpio7>;
310		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
311	};
312
313	wlcore: wlcore@2 {
314		compatible = "ti,wl1271";
315		reg = <2>;
316		interrupt-parent = <&gpio7>;
317		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
318		ref-clock-frequency = <38400000>;
319	};
320};
321
322&usdhc4 {
323	pinctrl-names = "default", "state_100mhz", "state_200mhz";
324	pinctrl-0 = <&pinctrl_usdhc4_50mhz>;
325	pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
326	pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
327	bus-width = <8>;
328	non-removable;
329	vmmc-supply = <&reg_1p8v>;
330	keep-power-in-suspend;
331	status = "okay";
332};
333
334&iomuxc {
335	pinctrl-names = "default";
336	pinctrl-0 = <&pinctrl_hog>;
337
338	pinctrl_audmux: audmuxgrp {
339		fsl,pins = <
340			MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD	0x1b0b0
341			MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC	0x1b0b0
342			MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS	0x1b0b0
343			MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD	0x1b0b0
344		>;
345	};
346
347	pinctrl_ecspi1: ecspi1grp {
348		fsl,pins = <
349			MX6SX_PAD_KEY_COL1__ECSPI1_MISO		0x100b1
350			MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI		0x100b1
351			MX6SX_PAD_KEY_COL0__ECSPI1_SCLK		0x100b1
352			MX6SX_PAD_KEY_ROW1__GPIO2_IO_16		0x0b0b1
353		>;
354	};
355
356	pinctrl_enet1: enet1grp {
357		fsl,pins = <
358			MX6SX_PAD_ENET1_MDIO__ENET1_MDIO	0x1b0b0
359			MX6SX_PAD_ENET1_MDC__ENET1_MDC		0x1b0b0
360			MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0	0x30b1
361			MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1	0x30b1
362			MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2	0x30b1
363			MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3	0x30b1
364			MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC	0x30b1
365			MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN	0x30b1
366			MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0	0x3081
367			MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1	0x3081
368			MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN	0x3081
369			MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2	0x3081
370			MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3	0x3081
371			MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK	0x3081
372			MX6SX_PAD_ENET2_CRS__GPIO2_IO_7		0xb0b0
373			MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4	0xb0b0
374			MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5	0xb0b0
375		>;
376	};
377
378	pinctrl_enet2: enet2grp {
379		fsl,pins = <
380			MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0	0x30b1
381			MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1	0x30b1
382			MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2	0x30b1
383			MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3	0x30b1
384			MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC	0x30b1
385			MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN	0x30b1
386			MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0	0x3081
387			MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1	0x3081
388			MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN	0x3081
389			MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2	0x3081
390			MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3	0x3081
391			MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK	0x3081
392			MX6SX_PAD_ENET2_COL__GPIO2_IO_6		0xb0b0
393			MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8	0xb0b0
394			MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9	0xb0b0
395		>;
396	};
397
398	pinctrl_flexcan1: flexcan1grp {
399		fsl,pins = <
400			MX6SX_PAD_QSPI1B_DQS__CAN1_TX		0x1b0b0
401			MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX		0x1b0b0
402			MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27	0x1b0b0
403			MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27	0x0b0b0
404		>;
405	};
406
407	pinctrl_flexcan2: flexcan2grp {
408		fsl,pins = <
409			MX6SX_PAD_QSPI1A_DQS__CAN2_TX		0x1b0b0
410			MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX		0x1b0b0
411			MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24	0x0b0b0
412		>;
413	};
414
415	pinctrl_hog: hoggrp {
416		fsl,pins = <
417			MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1	0x1b0b0
418			MX6SX_PAD_NAND_CLE__GPIO4_IO_3		0x1b0b0
419			MX6SX_PAD_NAND_RE_B__GPIO4_IO_12	0x1b0b0
420			MX6SX_PAD_NAND_WE_B__GPIO4_IO_14	0x1b0b0
421			MX6SX_PAD_NAND_WP_B__GPIO4_IO_15	0x1b0b0
422			MX6SX_PAD_NAND_READY_B__GPIO4_IO_13	0x1b0b0
423			MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16	0x1b0b0
424			MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17	0x1b0b0
425			MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18	0x1b0b0
426			MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19	0x1b0b0
427			MX6SX_PAD_SD1_CMD__CCM_CLKO1		0x000b0
428			MX6SX_PAD_SD3_DATA5__GPIO7_IO_7		0x1b0b0
429			/* Test points */
430			MX6SX_PAD_NAND_DATA04__GPIO4_IO_8	0x1b0b0
431			MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25	0x1b0b0
432		>;
433	};
434
435	pinctrl_i2c1: i2c1grp {
436		fsl,pins = <
437			MX6SX_PAD_GPIO1_IO00__I2C1_SCL		0x4001b8b1
438			MX6SX_PAD_GPIO1_IO01__I2C1_SDA		0x4001b8b1
439		>;
440	};
441
442	pinctrl_i2c2: i2c2grp {
443		fsl,pins = <
444			MX6SX_PAD_GPIO1_IO02__I2C2_SCL		0x4001b8b1
445			MX6SX_PAD_GPIO1_IO03__I2C2_SDA		0x4001b8b1
446		>;
447	};
448
449	pinctrl_i2c3: i2c3grp {
450		fsl,pins = <
451			MX6SX_PAD_KEY_COL4__I2C3_SCL		0x4001b8b1
452			MX6SX_PAD_KEY_ROW4__I2C3_SDA		0x4001b8b1
453		>;
454	};
455
456	pinctrl_pcie: pciegrp {
457		fsl,pins = <
458			MX6SX_PAD_NAND_DATA05__GPIO4_IO_9	0xb0b0
459			MX6SX_PAD_NAND_DATA06__GPIO4_IO_10	0xb0b0
460			MX6SX_PAD_NAND_DATA07__GPIO4_IO_11	0xb0b0
461		>;
462	};
463
464	pinctrl_pwm4: pwm4grp {
465		fsl,pins = <
466			MX6SX_PAD_GPIO1_IO13__PWM4_OUT		0x110b0
467		>;
468	};
469
470	pinctrl_reg_wlan: reg-wlangrp {
471		fsl,pins = <
472			MX6SX_PAD_SD3_DATA4__GPIO7_IO_6		0x1b0b0
473			MX6SX_PAD_GPIO1_IO11__CCM_CLKO1		0x000b0
474		>;
475	};
476
477	pinctrl_sgtl5000: sgtl5000grp {
478		fsl,pins = <
479			MX6SX_PAD_GPIO1_IO12__CCM_CLKO2		0x000b0
480			MX6SX_PAD_ENET1_COL__GPIO2_IO_0		0x1b0b0
481			MX6SX_PAD_ENET1_CRS__GPIO2_IO_1		0x1b0b0
482			MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22	0xb0b0
483		>;
484	};
485
486	pinctrl_uart1: uart1grp {
487		fsl,pins = <
488			MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX		0x1b0b1
489			MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX		0x1b0b1
490		>;
491	};
492
493	pinctrl_uart2: uart2grp {
494		fsl,pins = <
495			MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX		0x1b0b1
496			MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX		0x1b0b1
497		>;
498	};
499
500	pinctrl_uart3: uart3grp {
501		fsl,pins = <
502			MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX		0x1b0b1
503			MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX		0x1b0b1
504		>;
505	};
506
507	pinctrl_uart5: uart5grp {
508		fsl,pins = <
509			MX6SX_PAD_KEY_COL3__UART5_DCE_TX		0x1b0b1
510			MX6SX_PAD_KEY_ROW3__UART5_DCE_RX		0x1b0b1
511			MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS		0x1b0b1
512			MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS		0x1b0b1
513		>;
514	};
515
516	pinctrl_usbotg1: usbotg1grp {
517		fsl,pins = <
518			MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC	0x1b0b0
519			MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID	0x170b1
520		>;
521	};
522
523	pinctrl_usbotg1_vbus: usbotg1-vbusgrp {
524		fsl,pins = <
525			MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9	0x1b0b0
526		>;
527	};
528
529	pinctrl_usbotg2: usbotg2grp {
530		fsl,pins = <
531			MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26	0xb0b0
532		>;
533	};
534
535	pinctrl_usdhc2: usdhc2grp {
536		fsl,pins = <
537			MX6SX_PAD_SD2_CMD__USDHC2_CMD		0x17059
538			MX6SX_PAD_SD2_CLK__USDHC2_CLK		0x10059
539			MX6SX_PAD_SD2_DATA0__USDHC2_DATA0	0x17059
540			MX6SX_PAD_SD2_DATA1__USDHC2_DATA1	0x17059
541			MX6SX_PAD_SD2_DATA2__USDHC2_DATA2	0x17059
542			MX6SX_PAD_SD2_DATA3__USDHC2_DATA3	0x17059
543			MX6SX_PAD_KEY_COL2__GPIO2_IO_12		0x1b0b0
544		>;
545	};
546
547	pinctrl_usdhc3: usdhc3grp {
548		fsl,pins = <
549			MX6SX_PAD_SD3_CLK__USDHC3_CLK		0x10071
550			MX6SX_PAD_SD3_CMD__USDHC3_CMD		0x17071
551			MX6SX_PAD_SD3_DATA0__USDHC3_DATA0	0x17071
552			MX6SX_PAD_SD3_DATA1__USDHC3_DATA1	0x17071
553			MX6SX_PAD_SD3_DATA2__USDHC3_DATA2	0x17071
554			MX6SX_PAD_SD3_DATA3__USDHC3_DATA3	0x17071
555		>;
556	};
557
558	pinctrl_usdhc4_50mhz: usdhc4-50mhzgrp {
559		fsl,pins = <
560			MX6SX_PAD_SD4_CLK__USDHC4_CLK		0x10071
561			MX6SX_PAD_SD4_CMD__USDHC4_CMD		0x17071
562			MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B	0x17071
563			MX6SX_PAD_SD4_DATA0__USDHC4_DATA0	0x17071
564			MX6SX_PAD_SD4_DATA1__USDHC4_DATA1	0x17071
565			MX6SX_PAD_SD4_DATA2__USDHC4_DATA2	0x17071
566			MX6SX_PAD_SD4_DATA3__USDHC4_DATA3	0x17071
567			MX6SX_PAD_SD4_DATA4__USDHC4_DATA4	0x17071
568			MX6SX_PAD_SD4_DATA5__USDHC4_DATA5	0x17071
569			MX6SX_PAD_SD4_DATA6__USDHC4_DATA6	0x17071
570			MX6SX_PAD_SD4_DATA7__USDHC4_DATA7	0x17071
571		>;
572	};
573
574	pinctrl_usdhc4_100mhz: usdhc4-100mhzgrp {
575		fsl,pins = <
576			MX6SX_PAD_SD4_CLK__USDHC4_CLK		0x100b9
577			MX6SX_PAD_SD4_CMD__USDHC4_CMD		0x170b9
578			MX6SX_PAD_SD4_DATA0__USDHC4_DATA0	0x170b9
579			MX6SX_PAD_SD4_DATA1__USDHC4_DATA1	0x170b9
580			MX6SX_PAD_SD4_DATA2__USDHC4_DATA2	0x170b9
581			MX6SX_PAD_SD4_DATA3__USDHC4_DATA3	0x170b9
582			MX6SX_PAD_SD4_DATA4__USDHC4_DATA4	0x170b9
583			MX6SX_PAD_SD4_DATA5__USDHC4_DATA5	0x170b9
584			MX6SX_PAD_SD4_DATA6__USDHC4_DATA6	0x170b9
585			MX6SX_PAD_SD4_DATA7__USDHC4_DATA7	0x170b9
586		>;
587	};
588
589	pinctrl_usdhc4_200mhz: usdhc4-200mhzgrp {
590		fsl,pins = <
591			MX6SX_PAD_SD4_CLK__USDHC4_CLK		0x100f9
592			MX6SX_PAD_SD4_CMD__USDHC4_CMD		0x170f9
593			MX6SX_PAD_SD4_DATA0__USDHC4_DATA0	0x170f9
594			MX6SX_PAD_SD4_DATA1__USDHC4_DATA1	0x170f9
595			MX6SX_PAD_SD4_DATA2__USDHC4_DATA2	0x170f9
596			MX6SX_PAD_SD4_DATA3__USDHC4_DATA3	0x170f9
597			MX6SX_PAD_SD4_DATA4__USDHC4_DATA4	0x170f9
598			MX6SX_PAD_SD4_DATA5__USDHC4_DATA5	0x170f9
599			MX6SX_PAD_SD4_DATA6__USDHC4_DATA6	0x170f9
600			MX6SX_PAD_SD4_DATA7__USDHC4_DATA7	0x170f9
601		>;
602	};
603};
604