1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (c) 2020 thingy.jp.
4 * Author: Daniel Palmer <daniel@thingy.jp>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/mstar-msc313-mpll.h>
10
11/ {
12	#address-cells = <1>;
13	#size-cells = <1>;
14	interrupt-parent = <&gic>;
15
16	cpus: cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		cpu0: cpu@0 {
21			device_type = "cpu";
22			compatible = "arm,cortex-a7";
23			reg = <0x0>;
24		};
25	};
26
27	arch_timer {
28		compatible = "arm,armv7-timer";
29		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2)
30				| IRQ_TYPE_LEVEL_LOW)>,
31			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2)
32				| IRQ_TYPE_LEVEL_LOW)>,
33			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2)
34				| IRQ_TYPE_LEVEL_LOW)>,
35			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2)
36				| IRQ_TYPE_LEVEL_LOW)>;
37		/*
38		 * we shouldn't need this but the vendor
39		 * u-boot is broken
40		 */
41		clock-frequency = <6000000>;
42		arm,cpu-registers-not-fw-configured;
43	};
44
45	pmu: pmu {
46		compatible = "arm,cortex-a7-pmu";
47		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
48		interrupt-affinity = <&cpu0>;
49	};
50
51	clocks: clocks {
52		xtal: xtal {
53			#clock-cells = <0>;
54			compatible = "fixed-clock";
55			clock-frequency = <24000000>;
56		};
57
58		rtc_xtal: rtc_xtal {
59			#clock-cells = <0>;
60			compatible = "fixed-clock";
61			clock-frequency = <32768>;
62			status = "disabled";
63		};
64
65		xtal_div2: xtal_div2 {
66			#clock-cells = <0>;
67			compatible = "fixed-factor-clock";
68			clocks = <&xtal>;
69			clock-div = <2>;
70			clock-mult = <1>;
71		};
72	};
73
74	soc: soc {
75		compatible = "simple-bus";
76		#address-cells = <1>;
77		#size-cells = <1>;
78		ranges = <0x16001000 0x16001000 0x00007000>,
79			 <0x1f000000 0x1f000000 0x00400000>,
80			 <0xa0000000 0xa0000000 0x20000>;
81
82		gic: interrupt-controller@16001000 {
83			compatible = "arm,cortex-a7-gic";
84			reg = <0x16001000 0x1000>,
85			      <0x16002000 0x2000>,
86			      <0x16004000 0x2000>,
87			      <0x16006000 0x2000>;
88			#interrupt-cells = <3>;
89			interrupt-controller;
90			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2)
91					| IRQ_TYPE_LEVEL_LOW)>;
92		};
93
94		riu: bus@1f000000 {
95			compatible = "simple-bus";
96			reg = <0x1f000000 0x00400000>;
97			#address-cells = <1>;
98			#size-cells = <1>;
99			ranges = <0x0 0x1f000000 0x00400000>;
100
101			pmsleep: syscon@1c00 {
102				compatible = "mstar,msc313-pmsleep", "syscon";
103				reg = <0x1c00 0x100>;
104			};
105
106			reboot {
107				compatible = "syscon-reboot";
108				regmap = <&pmsleep>;
109				offset = <0xb8>;
110				mask = <0x79>;
111			};
112
113			rtc@2400 {
114				compatible = "mstar,msc313-rtc";
115				reg = <0x2400 0x40>;
116				clocks = <&xtal_div2>;
117				interrupts-extended = <&intc_irq GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
118			};
119
120			watchdog@6000 {
121				compatible = "mstar,msc313e-wdt";
122				reg = <0x6000 0x1f>;
123				clocks = <&xtal_div2>;
124			};
125
126
127			intc_fiq: interrupt-controller@201310 {
128				compatible = "mstar,mst-intc";
129				reg = <0x201310 0x40>;
130				#interrupt-cells = <3>;
131				interrupt-controller;
132				interrupt-parent = <&gic>;
133				mstar,irqs-map-range = <96 127>;
134			};
135
136			intc_irq: interrupt-controller@201350 {
137				compatible = "mstar,mst-intc";
138				reg = <0x201350 0x40>;
139				#interrupt-cells = <3>;
140				interrupt-controller;
141				interrupt-parent = <&gic>;
142				mstar,irqs-map-range = <32 95>;
143				mstar,intc-no-eoi;
144			};
145
146			l3bridge: l3bridge@204400 {
147				compatible = "mstar,l3bridge";
148				reg = <0x204400 0x200>;
149			};
150
151			mpll: mpll@206000 {
152				compatible = "mstar,msc313-mpll";
153				#clock-cells = <1>;
154				reg = <0x206000 0x200>;
155				clocks = <&xtal>;
156			};
157
158			gpio: gpio@207800 {
159				#gpio-cells = <2>;
160				reg = <0x207800 0x200>;
161				gpio-controller;
162				#interrupt-cells = <2>;
163				interrupt-controller;
164				interrupt-parent = <&intc_fiq>;
165				status = "disabled";
166			};
167
168			pm_uart: uart@221000 {
169				compatible = "ns16550a";
170				reg = <0x221000 0x100>;
171				reg-shift = <3>;
172				interrupts-extended = <&intc_irq GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
173				clock-frequency = <172000000>;
174				status = "disabled";
175			};
176		};
177
178		imi: sram@a0000000 {
179			compatible = "mmio-sram";
180			reg = <0xa0000000 0x10000>;
181		};
182	};
183};
184