1/* 2 * Device Tree Source for OMAP3 SoC 3 * 4 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 */ 10 11#include <dt-bindings/bus/ti-sysc.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/pinctrl/omap.h> 15 16/ { 17 compatible = "ti,omap3430", "ti,omap3"; 18 interrupt-parent = <&intc>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 chosen { }; 22 23 aliases { 24 i2c0 = &i2c1; 25 i2c1 = &i2c2; 26 i2c2 = &i2c3; 27 mmc0 = &mmc1; 28 mmc1 = &mmc2; 29 mmc2 = &mmc3; 30 serial0 = &uart1; 31 serial1 = &uart2; 32 serial2 = &uart3; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu@0 { 40 compatible = "arm,cortex-a8"; 41 device_type = "cpu"; 42 reg = <0x0>; 43 44 clocks = <&dpll1_ck>; 45 clock-names = "cpu"; 46 47 clock-latency = <300000>; /* From omap-cpufreq driver */ 48 }; 49 }; 50 51 pmu@54000000 { 52 compatible = "arm,cortex-a8-pmu"; 53 reg = <0x54000000 0x800000>; 54 interrupts = <3>; 55 ti,hwmods = "debugss"; 56 }; 57 58 /* 59 * The soc node represents the soc top level view. It is used for IPs 60 * that are not memory mapped in the MPU view or for the MPU itself. 61 */ 62 soc { 63 compatible = "ti,omap-infra"; 64 mpu { 65 compatible = "ti,omap3-mpu"; 66 ti,hwmods = "mpu"; 67 }; 68 69 iva: iva { 70 compatible = "ti,iva2.2"; 71 ti,hwmods = "iva"; 72 73 dsp { 74 compatible = "ti,omap3-c64"; 75 }; 76 }; 77 }; 78 79 /* 80 * XXX: Use a flat representation of the OMAP3 interconnect. 81 * The real OMAP interconnect network is quite complex. 82 * Since it will not bring real advantage to represent that in DT for 83 * the moment, just use a fake OCP bus entry to represent the whole bus 84 * hierarchy. 85 */ 86 ocp@68000000 { 87 compatible = "ti,omap3-l3-smx", "simple-bus"; 88 reg = <0x68000000 0x10000>; 89 interrupts = <9 10>; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 ranges; 93 ti,hwmods = "l3_main"; 94 95 l4_core: l4@48000000 { 96 compatible = "ti,omap3-l4-core", "simple-bus"; 97 #address-cells = <1>; 98 #size-cells = <1>; 99 ranges = <0 0x48000000 0x1000000>; 100 101 scm: scm@2000 { 102 compatible = "ti,omap3-scm", "simple-bus"; 103 reg = <0x2000 0x2000>; 104 #address-cells = <1>; 105 #size-cells = <1>; 106 ranges = <0 0x2000 0x2000>; 107 108 omap3_pmx_core: pinmux@30 { 109 compatible = "ti,omap3-padconf", 110 "pinctrl-single"; 111 reg = <0x30 0x238>; 112 #address-cells = <1>; 113 #size-cells = <0>; 114 #pinctrl-cells = <1>; 115 #interrupt-cells = <1>; 116 interrupt-controller; 117 pinctrl-single,register-width = <16>; 118 pinctrl-single,function-mask = <0xff1f>; 119 }; 120 121 scm_conf: scm_conf@270 { 122 compatible = "syscon", "simple-bus"; 123 reg = <0x270 0x330>; 124 #address-cells = <1>; 125 #size-cells = <1>; 126 ranges = <0 0x270 0x330>; 127 128 pbias_regulator: pbias_regulator@2b0 { 129 compatible = "ti,pbias-omap3", "ti,pbias-omap"; 130 reg = <0x2b0 0x4>; 131 syscon = <&scm_conf>; 132 pbias_mmc_reg: pbias_mmc_omap2430 { 133 regulator-name = "pbias_mmc_omap2430"; 134 regulator-min-microvolt = <1800000>; 135 regulator-max-microvolt = <3000000>; 136 }; 137 }; 138 139 scm_clocks: clocks { 140 #address-cells = <1>; 141 #size-cells = <0>; 142 }; 143 }; 144 145 scm_clockdomains: clockdomains { 146 }; 147 148 omap3_pmx_wkup: pinmux@a00 { 149 compatible = "ti,omap3-padconf", 150 "pinctrl-single"; 151 reg = <0xa00 0x5c>; 152 #address-cells = <1>; 153 #size-cells = <0>; 154 #pinctrl-cells = <1>; 155 #interrupt-cells = <1>; 156 interrupt-controller; 157 pinctrl-single,register-width = <16>; 158 pinctrl-single,function-mask = <0xff1f>; 159 }; 160 }; 161 }; 162 163 aes1_target: target-module@480a6000 { 164 compatible = "ti,sysc-omap2", "ti,sysc"; 165 reg = <0x480a6044 0x4>, 166 <0x480a6048 0x4>, 167 <0x480a604c 0x4>; 168 reg-names = "rev", "sysc", "syss"; 169 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; 170 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 171 <SYSC_IDLE_NO>, 172 <SYSC_IDLE_SMART>; 173 ti,syss-mask = <1>; 174 clocks = <&aes1_ick>; 175 clock-names = "ick"; 176 #address-cells = <1>; 177 #size-cells = <1>; 178 ranges = <0 0x480a6000 0x2000>; 179 180 aes1: aes1@0 { 181 compatible = "ti,omap3-aes"; 182 reg = <0 0x50>; 183 interrupts = <0>; 184 dmas = <&sdma 9 &sdma 10>; 185 dma-names = "tx", "rx"; 186 }; 187 }; 188 189 aes2_target: target-module@480c5000 { 190 compatible = "ti,sysc-omap2", "ti,sysc"; 191 reg = <0x480c5044 0x4>, 192 <0x480c5048 0x4>, 193 <0x480c504c 0x4>; 194 reg-names = "rev", "sysc", "syss"; 195 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; 196 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 197 <SYSC_IDLE_NO>, 198 <SYSC_IDLE_SMART>; 199 ti,syss-mask = <1>; 200 clocks = <&aes2_ick>; 201 clock-names = "ick"; 202 #address-cells = <1>; 203 #size-cells = <1>; 204 ranges = <0 0x480c5000 0x2000>; 205 206 aes2: aes2@0 { 207 compatible = "ti,omap3-aes"; 208 reg = <0 0x50>; 209 interrupts = <0>; 210 dmas = <&sdma 65 &sdma 66>; 211 dma-names = "tx", "rx"; 212 }; 213 }; 214 215 prm: prm@48306000 { 216 compatible = "ti,omap3-prm"; 217 reg = <0x48306000 0x4000>; 218 interrupts = <11>; 219 220 prm_clocks: clocks { 221 #address-cells = <1>; 222 #size-cells = <0>; 223 }; 224 225 prm_clockdomains: clockdomains { 226 }; 227 }; 228 229 cm: cm@48004000 { 230 compatible = "ti,omap3-cm"; 231 reg = <0x48004000 0x4000>; 232 233 cm_clocks: clocks { 234 #address-cells = <1>; 235 #size-cells = <0>; 236 }; 237 238 cm_clockdomains: clockdomains { 239 }; 240 }; 241 242 target-module@48320000 { 243 compatible = "ti,sysc-omap2", "ti,sysc"; 244 reg = <0x48320000 0x4>, 245 <0x48320004 0x4>; 246 reg-names = "rev", "sysc"; 247 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 248 <SYSC_IDLE_NO>; 249 clocks = <&wkup_32k_fck>, <&omap_32ksync_ick>; 250 clock-names = "fck", "ick"; 251 #address-cells = <1>; 252 #size-cells = <1>; 253 ranges = <0x0 0x48320000 0x1000>; 254 255 counter32k: counter@0 { 256 compatible = "ti,omap-counter32k"; 257 reg = <0x0 0x20>; 258 }; 259 }; 260 261 intc: interrupt-controller@48200000 { 262 compatible = "ti,omap3-intc"; 263 interrupt-controller; 264 #interrupt-cells = <1>; 265 reg = <0x48200000 0x1000>; 266 }; 267 268 target-module@48056000 { 269 compatible = "ti,sysc-omap2", "ti,sysc"; 270 reg = <0x48056000 0x4>, 271 <0x4805602c 0x4>, 272 <0x48056028 0x4>; 273 reg-names = "rev", "sysc", "syss"; 274 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 275 SYSC_OMAP2_EMUFREE | 276 SYSC_OMAP2_SOFTRESET | 277 SYSC_OMAP2_AUTOIDLE)>; 278 ti,sysc-midle = <SYSC_IDLE_FORCE>, 279 <SYSC_IDLE_NO>, 280 <SYSC_IDLE_SMART>; 281 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 282 <SYSC_IDLE_NO>, 283 <SYSC_IDLE_SMART>; 284 ti,syss-mask = <1>; 285 /* Domains (V, P, C): core, core_pwrdm, core_l3_clkdm */ 286 clocks = <&core_l3_ick>; 287 clock-names = "ick"; 288 #address-cells = <1>; 289 #size-cells = <1>; 290 ranges = <0 0x48056000 0x1000>; 291 292 sdma: dma-controller@0 { 293 compatible = "ti,omap3430-sdma", "ti,omap-sdma"; 294 reg = <0x0 0x1000>; 295 interrupts = <12>, 296 <13>, 297 <14>, 298 <15>; 299 #dma-cells = <1>; 300 dma-channels = <32>; 301 dma-requests = <96>; 302 }; 303 }; 304 305 gpio1: gpio@48310000 { 306 compatible = "ti,omap3-gpio"; 307 reg = <0x48310000 0x200>; 308 interrupts = <29>; 309 ti,hwmods = "gpio1"; 310 ti,gpio-always-on; 311 gpio-controller; 312 #gpio-cells = <2>; 313 interrupt-controller; 314 #interrupt-cells = <2>; 315 }; 316 317 gpio2: gpio@49050000 { 318 compatible = "ti,omap3-gpio"; 319 reg = <0x49050000 0x200>; 320 interrupts = <30>; 321 ti,hwmods = "gpio2"; 322 gpio-controller; 323 #gpio-cells = <2>; 324 interrupt-controller; 325 #interrupt-cells = <2>; 326 }; 327 328 gpio3: gpio@49052000 { 329 compatible = "ti,omap3-gpio"; 330 reg = <0x49052000 0x200>; 331 interrupts = <31>; 332 ti,hwmods = "gpio3"; 333 gpio-controller; 334 #gpio-cells = <2>; 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 }; 338 339 gpio4: gpio@49054000 { 340 compatible = "ti,omap3-gpio"; 341 reg = <0x49054000 0x200>; 342 interrupts = <32>; 343 ti,hwmods = "gpio4"; 344 gpio-controller; 345 #gpio-cells = <2>; 346 interrupt-controller; 347 #interrupt-cells = <2>; 348 }; 349 350 gpio5: gpio@49056000 { 351 compatible = "ti,omap3-gpio"; 352 reg = <0x49056000 0x200>; 353 interrupts = <33>; 354 ti,hwmods = "gpio5"; 355 gpio-controller; 356 #gpio-cells = <2>; 357 interrupt-controller; 358 #interrupt-cells = <2>; 359 }; 360 361 gpio6: gpio@49058000 { 362 compatible = "ti,omap3-gpio"; 363 reg = <0x49058000 0x200>; 364 interrupts = <34>; 365 ti,hwmods = "gpio6"; 366 gpio-controller; 367 #gpio-cells = <2>; 368 interrupt-controller; 369 #interrupt-cells = <2>; 370 }; 371 372 uart1: serial@4806a000 { 373 compatible = "ti,omap3-uart"; 374 reg = <0x4806a000 0x2000>; 375 interrupts-extended = <&intc 72>; 376 dmas = <&sdma 49 &sdma 50>; 377 dma-names = "tx", "rx"; 378 ti,hwmods = "uart1"; 379 clock-frequency = <48000000>; 380 }; 381 382 uart2: serial@4806c000 { 383 compatible = "ti,omap3-uart"; 384 reg = <0x4806c000 0x400>; 385 interrupts-extended = <&intc 73>; 386 dmas = <&sdma 51 &sdma 52>; 387 dma-names = "tx", "rx"; 388 ti,hwmods = "uart2"; 389 clock-frequency = <48000000>; 390 }; 391 392 uart3: serial@49020000 { 393 compatible = "ti,omap3-uart"; 394 reg = <0x49020000 0x400>; 395 interrupts-extended = <&intc 74>; 396 dmas = <&sdma 53 &sdma 54>; 397 dma-names = "tx", "rx"; 398 ti,hwmods = "uart3"; 399 clock-frequency = <48000000>; 400 }; 401 402 i2c1: i2c@48070000 { 403 compatible = "ti,omap3-i2c"; 404 reg = <0x48070000 0x80>; 405 interrupts = <56>; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 ti,hwmods = "i2c1"; 409 }; 410 411 i2c2: i2c@48072000 { 412 compatible = "ti,omap3-i2c"; 413 reg = <0x48072000 0x80>; 414 interrupts = <57>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 ti,hwmods = "i2c2"; 418 }; 419 420 i2c3: i2c@48060000 { 421 compatible = "ti,omap3-i2c"; 422 reg = <0x48060000 0x80>; 423 interrupts = <61>; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 ti,hwmods = "i2c3"; 427 }; 428 429 mailbox: mailbox@48094000 { 430 compatible = "ti,omap3-mailbox"; 431 ti,hwmods = "mailbox"; 432 reg = <0x48094000 0x200>; 433 interrupts = <26>; 434 #mbox-cells = <1>; 435 ti,mbox-num-users = <2>; 436 ti,mbox-num-fifos = <2>; 437 mbox_dsp: mbox-dsp { 438 ti,mbox-tx = <0 0 0>; 439 ti,mbox-rx = <1 0 0>; 440 }; 441 }; 442 443 mcspi1: spi@48098000 { 444 compatible = "ti,omap2-mcspi"; 445 reg = <0x48098000 0x100>; 446 interrupts = <65>; 447 #address-cells = <1>; 448 #size-cells = <0>; 449 ti,hwmods = "mcspi1"; 450 ti,spi-num-cs = <4>; 451 dmas = <&sdma 35>, 452 <&sdma 36>, 453 <&sdma 37>, 454 <&sdma 38>, 455 <&sdma 39>, 456 <&sdma 40>, 457 <&sdma 41>, 458 <&sdma 42>; 459 dma-names = "tx0", "rx0", "tx1", "rx1", 460 "tx2", "rx2", "tx3", "rx3"; 461 }; 462 463 mcspi2: spi@4809a000 { 464 compatible = "ti,omap2-mcspi"; 465 reg = <0x4809a000 0x100>; 466 interrupts = <66>; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 ti,hwmods = "mcspi2"; 470 ti,spi-num-cs = <2>; 471 dmas = <&sdma 43>, 472 <&sdma 44>, 473 <&sdma 45>, 474 <&sdma 46>; 475 dma-names = "tx0", "rx0", "tx1", "rx1"; 476 }; 477 478 mcspi3: spi@480b8000 { 479 compatible = "ti,omap2-mcspi"; 480 reg = <0x480b8000 0x100>; 481 interrupts = <91>; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 ti,hwmods = "mcspi3"; 485 ti,spi-num-cs = <2>; 486 dmas = <&sdma 15>, 487 <&sdma 16>, 488 <&sdma 23>, 489 <&sdma 24>; 490 dma-names = "tx0", "rx0", "tx1", "rx1"; 491 }; 492 493 mcspi4: spi@480ba000 { 494 compatible = "ti,omap2-mcspi"; 495 reg = <0x480ba000 0x100>; 496 interrupts = <48>; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 ti,hwmods = "mcspi4"; 500 ti,spi-num-cs = <1>; 501 dmas = <&sdma 70>, <&sdma 71>; 502 dma-names = "tx0", "rx0"; 503 }; 504 505 hdqw1w: 1w@480b2000 { 506 compatible = "ti,omap3-1w"; 507 reg = <0x480b2000 0x1000>; 508 interrupts = <58>; 509 ti,hwmods = "hdq1w"; 510 }; 511 512 mmc1: mmc@4809c000 { 513 compatible = "ti,omap3-hsmmc"; 514 reg = <0x4809c000 0x200>; 515 interrupts = <83>; 516 ti,hwmods = "mmc1"; 517 ti,dual-volt; 518 dmas = <&sdma 61>, <&sdma 62>; 519 dma-names = "tx", "rx"; 520 pbias-supply = <&pbias_mmc_reg>; 521 }; 522 523 mmc2: mmc@480b4000 { 524 compatible = "ti,omap3-hsmmc"; 525 reg = <0x480b4000 0x200>; 526 interrupts = <86>; 527 ti,hwmods = "mmc2"; 528 dmas = <&sdma 47>, <&sdma 48>; 529 dma-names = "tx", "rx"; 530 }; 531 532 mmc3: mmc@480ad000 { 533 compatible = "ti,omap3-hsmmc"; 534 reg = <0x480ad000 0x200>; 535 interrupts = <94>; 536 ti,hwmods = "mmc3"; 537 dmas = <&sdma 77>, <&sdma 78>; 538 dma-names = "tx", "rx"; 539 }; 540 541 mmu_isp: mmu@480bd400 { 542 #iommu-cells = <0>; 543 compatible = "ti,omap2-iommu"; 544 reg = <0x480bd400 0x80>; 545 interrupts = <24>; 546 ti,hwmods = "mmu_isp"; 547 ti,#tlb-entries = <8>; 548 }; 549 550 mmu_iva: mmu@5d000000 { 551 #iommu-cells = <0>; 552 compatible = "ti,omap2-iommu"; 553 reg = <0x5d000000 0x80>; 554 interrupts = <28>; 555 ti,hwmods = "mmu_iva"; 556 status = "disabled"; 557 }; 558 559 wdt2: wdt@48314000 { 560 compatible = "ti,omap3-wdt"; 561 reg = <0x48314000 0x80>; 562 ti,hwmods = "wd_timer2"; 563 }; 564 565 mcbsp1: mcbsp@48074000 { 566 compatible = "ti,omap3-mcbsp"; 567 reg = <0x48074000 0xff>; 568 reg-names = "mpu"; 569 interrupts = <16>, /* OCP compliant interrupt */ 570 <59>, /* TX interrupt */ 571 <60>; /* RX interrupt */ 572 interrupt-names = "common", "tx", "rx"; 573 ti,buffer-size = <128>; 574 ti,hwmods = "mcbsp1"; 575 dmas = <&sdma 31>, 576 <&sdma 32>; 577 dma-names = "tx", "rx"; 578 clocks = <&mcbsp1_fck>; 579 clock-names = "fck"; 580 status = "disabled"; 581 }; 582 583 /* Likely needs to be tagged disabled on HS devices */ 584 rng_target: target-module@480a0000 { 585 compatible = "ti,sysc-omap2", "ti,sysc"; 586 reg = <0x480a003c 0x4>, 587 <0x480a0040 0x4>, 588 <0x480a0044 0x4>; 589 reg-names = "rev", "sysc", "syss"; 590 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; 591 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 592 <SYSC_IDLE_NO>; 593 ti,syss-mask = <1>; 594 clocks = <&rng_ick>; 595 clock-names = "ick"; 596 #address-cells = <1>; 597 #size-cells = <1>; 598 ranges = <0 0x480a0000 0x2000>; 599 600 rng: rng@0 { 601 compatible = "ti,omap2-rng"; 602 reg = <0x0 0x2000>; 603 interrupts = <52>; 604 }; 605 }; 606 607 mcbsp2: mcbsp@49022000 { 608 compatible = "ti,omap3-mcbsp"; 609 reg = <0x49022000 0xff>, 610 <0x49028000 0xff>; 611 reg-names = "mpu", "sidetone"; 612 interrupts = <17>, /* OCP compliant interrupt */ 613 <62>, /* TX interrupt */ 614 <63>, /* RX interrupt */ 615 <4>; /* Sidetone */ 616 interrupt-names = "common", "tx", "rx", "sidetone"; 617 ti,buffer-size = <1280>; 618 ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; 619 dmas = <&sdma 33>, 620 <&sdma 34>; 621 dma-names = "tx", "rx"; 622 clocks = <&mcbsp2_fck>, <&mcbsp2_ick>; 623 clock-names = "fck", "ick"; 624 status = "disabled"; 625 }; 626 627 mcbsp3: mcbsp@49024000 { 628 compatible = "ti,omap3-mcbsp"; 629 reg = <0x49024000 0xff>, 630 <0x4902a000 0xff>; 631 reg-names = "mpu", "sidetone"; 632 interrupts = <22>, /* OCP compliant interrupt */ 633 <89>, /* TX interrupt */ 634 <90>, /* RX interrupt */ 635 <5>; /* Sidetone */ 636 interrupt-names = "common", "tx", "rx", "sidetone"; 637 ti,buffer-size = <128>; 638 ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; 639 dmas = <&sdma 17>, 640 <&sdma 18>; 641 dma-names = "tx", "rx"; 642 clocks = <&mcbsp3_fck>, <&mcbsp3_ick>; 643 clock-names = "fck", "ick"; 644 status = "disabled"; 645 }; 646 647 mcbsp4: mcbsp@49026000 { 648 compatible = "ti,omap3-mcbsp"; 649 reg = <0x49026000 0xff>; 650 reg-names = "mpu"; 651 interrupts = <23>, /* OCP compliant interrupt */ 652 <54>, /* TX interrupt */ 653 <55>; /* RX interrupt */ 654 interrupt-names = "common", "tx", "rx"; 655 ti,buffer-size = <128>; 656 ti,hwmods = "mcbsp4"; 657 dmas = <&sdma 19>, 658 <&sdma 20>; 659 dma-names = "tx", "rx"; 660 clocks = <&mcbsp4_fck>; 661 clock-names = "fck"; 662 #sound-dai-cells = <0>; 663 status = "disabled"; 664 }; 665 666 mcbsp5: mcbsp@48096000 { 667 compatible = "ti,omap3-mcbsp"; 668 reg = <0x48096000 0xff>; 669 reg-names = "mpu"; 670 interrupts = <27>, /* OCP compliant interrupt */ 671 <81>, /* TX interrupt */ 672 <82>; /* RX interrupt */ 673 interrupt-names = "common", "tx", "rx"; 674 ti,buffer-size = <128>; 675 ti,hwmods = "mcbsp5"; 676 dmas = <&sdma 21>, 677 <&sdma 22>; 678 dma-names = "tx", "rx"; 679 clocks = <&mcbsp5_fck>; 680 clock-names = "fck"; 681 status = "disabled"; 682 }; 683 684 sham: sham@480c3000 { 685 compatible = "ti,omap3-sham"; 686 ti,hwmods = "sham"; 687 reg = <0x480c3000 0x64>; 688 interrupts = <49>; 689 dmas = <&sdma 69>; 690 dma-names = "rx"; 691 }; 692 693 timer1_target: target-module@48318000 { 694 compatible = "ti,sysc-omap2-timer", "ti,sysc"; 695 reg = <0x48318000 0x4>, 696 <0x48318010 0x4>, 697 <0x48318014 0x4>; 698 reg-names = "rev", "sysc", "syss"; 699 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 700 SYSC_OMAP2_EMUFREE | 701 SYSC_OMAP2_ENAWAKEUP | 702 SYSC_OMAP2_SOFTRESET | 703 SYSC_OMAP2_AUTOIDLE)>; 704 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 705 <SYSC_IDLE_NO>, 706 <SYSC_IDLE_SMART>; 707 ti,syss-mask = <1>; 708 clocks = <&gpt1_fck>, <&gpt1_ick>; 709 clock-names = "fck", "ick"; 710 #address-cells = <1>; 711 #size-cells = <1>; 712 ranges = <0x0 0x48318000 0x1000>; 713 714 timer1: timer@0 { 715 compatible = "ti,omap3430-timer"; 716 reg = <0x0 0x80>; 717 clocks = <&gpt1_fck>; 718 clock-names = "fck"; 719 interrupts = <37>; 720 ti,timer-alwon; 721 }; 722 }; 723 724 timer2_target: target-module@49032000 { 725 compatible = "ti,sysc-omap2-timer", "ti,sysc"; 726 reg = <0x49032000 0x4>, 727 <0x49032010 0x4>, 728 <0x49032014 0x4>; 729 reg-names = "rev", "sysc", "syss"; 730 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 731 SYSC_OMAP2_EMUFREE | 732 SYSC_OMAP2_ENAWAKEUP | 733 SYSC_OMAP2_SOFTRESET | 734 SYSC_OMAP2_AUTOIDLE)>; 735 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 736 <SYSC_IDLE_NO>, 737 <SYSC_IDLE_SMART>; 738 ti,syss-mask = <1>; 739 clocks = <&gpt2_fck>, <&gpt2_ick>; 740 clock-names = "fck", "ick"; 741 #address-cells = <1>; 742 #size-cells = <1>; 743 ranges = <0x0 0x49032000 0x1000>; 744 745 timer2: timer@0 { 746 compatible = "ti,omap3430-timer"; 747 reg = <0 0x400>; 748 interrupts = <38>; 749 }; 750 }; 751 752 timer3: timer@49034000 { 753 compatible = "ti,omap3430-timer"; 754 reg = <0x49034000 0x400>; 755 interrupts = <39>; 756 ti,hwmods = "timer3"; 757 }; 758 759 timer4: timer@49036000 { 760 compatible = "ti,omap3430-timer"; 761 reg = <0x49036000 0x400>; 762 interrupts = <40>; 763 ti,hwmods = "timer4"; 764 }; 765 766 timer5: timer@49038000 { 767 compatible = "ti,omap3430-timer"; 768 reg = <0x49038000 0x400>; 769 interrupts = <41>; 770 ti,hwmods = "timer5"; 771 ti,timer-dsp; 772 }; 773 774 timer6: timer@4903a000 { 775 compatible = "ti,omap3430-timer"; 776 reg = <0x4903a000 0x400>; 777 interrupts = <42>; 778 ti,hwmods = "timer6"; 779 ti,timer-dsp; 780 }; 781 782 timer7: timer@4903c000 { 783 compatible = "ti,omap3430-timer"; 784 reg = <0x4903c000 0x400>; 785 interrupts = <43>; 786 ti,hwmods = "timer7"; 787 ti,timer-dsp; 788 }; 789 790 timer8: timer@4903e000 { 791 compatible = "ti,omap3430-timer"; 792 reg = <0x4903e000 0x400>; 793 interrupts = <44>; 794 ti,hwmods = "timer8"; 795 ti,timer-pwm; 796 ti,timer-dsp; 797 }; 798 799 timer9: timer@49040000 { 800 compatible = "ti,omap3430-timer"; 801 reg = <0x49040000 0x400>; 802 interrupts = <45>; 803 ti,hwmods = "timer9"; 804 ti,timer-pwm; 805 }; 806 807 timer10: timer@48086000 { 808 compatible = "ti,omap3430-timer"; 809 reg = <0x48086000 0x400>; 810 interrupts = <46>; 811 ti,hwmods = "timer10"; 812 ti,timer-pwm; 813 }; 814 815 timer11: timer@48088000 { 816 compatible = "ti,omap3430-timer"; 817 reg = <0x48088000 0x400>; 818 interrupts = <47>; 819 ti,hwmods = "timer11"; 820 ti,timer-pwm; 821 }; 822 823 timer12_target: target-module@48304000 { 824 compatible = "ti,sysc-omap2-timer", "ti,sysc"; 825 reg = <0x48304000 0x4>, 826 <0x48304010 0x4>, 827 <0x48304014 0x4>; 828 reg-names = "rev", "sysc", "syss"; 829 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 830 SYSC_OMAP2_EMUFREE | 831 SYSC_OMAP2_ENAWAKEUP | 832 SYSC_OMAP2_SOFTRESET | 833 SYSC_OMAP2_AUTOIDLE)>; 834 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 835 <SYSC_IDLE_NO>, 836 <SYSC_IDLE_SMART>; 837 ti,syss-mask = <1>; 838 clocks = <&gpt12_fck>, <&gpt12_ick>; 839 clock-names = "fck", "ick"; 840 #address-cells = <1>; 841 #size-cells = <1>; 842 ranges = <0x0 0x48304000 0x1000>; 843 844 timer12: timer@0 { 845 compatible = "ti,omap3430-timer"; 846 reg = <0 0x400>; 847 interrupts = <95>; 848 ti,timer-alwon; 849 ti,timer-secure; 850 }; 851 }; 852 853 usbhstll: usbhstll@48062000 { 854 compatible = "ti,usbhs-tll"; 855 reg = <0x48062000 0x1000>; 856 interrupts = <78>; 857 ti,hwmods = "usb_tll_hs"; 858 }; 859 860 usbhshost: usbhshost@48064000 { 861 compatible = "ti,usbhs-host"; 862 reg = <0x48064000 0x400>; 863 ti,hwmods = "usb_host_hs"; 864 #address-cells = <1>; 865 #size-cells = <1>; 866 ranges; 867 868 usbhsohci: ohci@48064400 { 869 compatible = "ti,ohci-omap3"; 870 reg = <0x48064400 0x400>; 871 interrupts = <76>; 872 remote-wakeup-connected; 873 }; 874 875 usbhsehci: ehci@48064800 { 876 compatible = "ti,ehci-omap"; 877 reg = <0x48064800 0x400>; 878 interrupts = <77>; 879 }; 880 }; 881 882 gpmc: gpmc@6e000000 { 883 compatible = "ti,omap3430-gpmc"; 884 ti,hwmods = "gpmc"; 885 reg = <0x6e000000 0x02d0>; 886 interrupts = <20>; 887 dmas = <&sdma 4>; 888 dma-names = "rxtx"; 889 gpmc,num-cs = <8>; 890 gpmc,num-waitpins = <4>; 891 #address-cells = <2>; 892 #size-cells = <1>; 893 interrupt-controller; 894 #interrupt-cells = <2>; 895 gpio-controller; 896 #gpio-cells = <2>; 897 }; 898 899 usb_otg_hs: usb_otg_hs@480ab000 { 900 compatible = "ti,omap3-musb"; 901 reg = <0x480ab000 0x1000>; 902 interrupts = <92>, <93>; 903 interrupt-names = "mc", "dma"; 904 ti,hwmods = "usb_otg_hs"; 905 multipoint = <1>; 906 num-eps = <16>; 907 ram-bits = <12>; 908 }; 909 910 dss: dss@48050000 { 911 compatible = "ti,omap3-dss"; 912 reg = <0x48050000 0x200>; 913 status = "disabled"; 914 ti,hwmods = "dss_core"; 915 clocks = <&dss1_alwon_fck>; 916 clock-names = "fck"; 917 #address-cells = <1>; 918 #size-cells = <1>; 919 ranges; 920 921 dispc@48050400 { 922 compatible = "ti,omap3-dispc"; 923 reg = <0x48050400 0x400>; 924 interrupts = <25>; 925 ti,hwmods = "dss_dispc"; 926 clocks = <&dss1_alwon_fck>; 927 clock-names = "fck"; 928 }; 929 930 dsi: encoder@4804fc00 { 931 compatible = "ti,omap3-dsi"; 932 reg = <0x4804fc00 0x200>, 933 <0x4804fe00 0x40>, 934 <0x4804ff00 0x20>; 935 reg-names = "proto", "phy", "pll"; 936 interrupts = <25>; 937 status = "disabled"; 938 ti,hwmods = "dss_dsi1"; 939 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>; 940 clock-names = "fck", "sys_clk"; 941 942 #address-cells = <1>; 943 #size-cells = <0>; 944 }; 945 946 rfbi: encoder@48050800 { 947 compatible = "ti,omap3-rfbi"; 948 reg = <0x48050800 0x100>; 949 status = "disabled"; 950 ti,hwmods = "dss_rfbi"; 951 clocks = <&dss1_alwon_fck>, <&dss_ick>; 952 clock-names = "fck", "ick"; 953 }; 954 955 venc: encoder@48050c00 { 956 compatible = "ti,omap3-venc"; 957 reg = <0x48050c00 0x100>; 958 status = "disabled"; 959 ti,hwmods = "dss_venc"; 960 clocks = <&dss_tv_fck>; 961 clock-names = "fck"; 962 }; 963 }; 964 965 ssi: ssi-controller@48058000 { 966 compatible = "ti,omap3-ssi"; 967 ti,hwmods = "ssi"; 968 969 status = "disabled"; 970 971 reg = <0x48058000 0x1000>, 972 <0x48059000 0x1000>; 973 reg-names = "sys", 974 "gdd"; 975 976 interrupts = <71>; 977 interrupt-names = "gdd_mpu"; 978 979 #address-cells = <1>; 980 #size-cells = <1>; 981 ranges; 982 983 ssi_port1: ssi-port@4805a000 { 984 compatible = "ti,omap3-ssi-port"; 985 986 reg = <0x4805a000 0x800>, 987 <0x4805a800 0x800>; 988 reg-names = "tx", 989 "rx"; 990 991 interrupts = <67>, 992 <68>; 993 }; 994 995 ssi_port2: ssi-port@4805b000 { 996 compatible = "ti,omap3-ssi-port"; 997 998 reg = <0x4805b000 0x800>, 999 <0x4805b800 0x800>; 1000 reg-names = "tx", 1001 "rx"; 1002 1003 interrupts = <69>, 1004 <70>; 1005 }; 1006 }; 1007 }; 1008}; 1009 1010#include "omap3xxx-clocks.dtsi" 1011 1012/* Preferred always-on timer for clockevent. Some boards must use dmtimer12 */ 1013&timer1_target { 1014 ti,no-reset-on-init; 1015 ti,no-idle; 1016 timer@0 { 1017 assigned-clocks = <&gpt1_fck>; 1018 assigned-clock-parents = <&omap_32k_fck>; 1019 }; 1020}; 1021