1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the iWave-RZ/G1H Qseven board development
4 * platform with camera daughter board
5 *
6 * Copyright (C) 2020 Renesas Electronics Corp.
7 */
8
9/dts-v1/;
10#include "r8a7742-iwg21d-q7.dts"
11
12/ {
13	model = "iWave Systems RZ/G1H Qseven development platform with camera add-on";
14	compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742";
15
16	aliases {
17		serial0 = &scif0;
18		serial1 = &scif1;
19		serial3 = &scifb1;
20		serial5 = &hscif0;
21		ethernet1 = &ether;
22	};
23
24	mclk_cam1: mclk-cam1 {
25		compatible = "fixed-clock";
26		#clock-cells = <0>;
27		clock-frequency = <26000000>;
28	};
29
30	mclk_cam2: mclk-cam2 {
31		compatible = "fixed-clock";
32		#clock-cells = <0>;
33		clock-frequency = <26000000>;
34	};
35
36	mclk_cam3: mclk-cam3 {
37		compatible = "fixed-clock";
38		#clock-cells = <0>;
39		clock-frequency = <26000000>;
40	};
41
42	mclk_cam4: mclk-cam4 {
43		compatible = "fixed-clock";
44		#clock-cells = <0>;
45		clock-frequency = <26000000>;
46	};
47};
48
49&avb {
50	/* Pins shared with VIN0, keep status disabled */
51	status = "disabled";
52};
53
54&can0 {
55	pinctrl-0 = <&can0_pins>;
56	pinctrl-names = "default";
57	status = "okay";
58};
59
60&ether {
61	pinctrl-0 = <&ether_pins>;
62	pinctrl-names = "default";
63
64	phy-handle = <&phy1>;
65	renesas,ether-link-active-low;
66	status = "okay";
67
68	phy1: ethernet-phy@1 {
69		compatible = "ethernet-phy-id0022.1560",
70			     "ethernet-phy-ieee802.3-c22";
71		reg = <1>;
72		micrel,led-mode = <1>;
73	};
74};
75
76&gpio0 {
77	/* Disable hogging GP0_18 to output LOW */
78	/delete-node/ qspi_en;
79
80	/* Hog GP0_18 to output HIGH to enable VIN2 */
81	vin2_en {
82		gpio-hog;
83		gpios = <18 GPIO_ACTIVE_HIGH>;
84		output-high;
85		line-name = "VIN2_EN";
86	};
87};
88
89&hscif0 {
90	pinctrl-0 = <&hscif0_pins>;
91	pinctrl-names = "default";
92	uart-has-rtscts;
93	status = "okay";
94};
95
96&i2c1 {
97	pinctrl-0 = <&i2c1_pins>;
98	pinctrl-names = "default";
99
100	/* status set to "okay" when needed by camera configuration below */
101	clock-frequency = <400000>;
102};
103
104&i2c3 {
105	pinctrl-0 = <&i2c3_pins>;
106	pinctrl-names = "default";
107
108	/* status set to "okay" when needed by camera configuration below */
109	clock-frequency = <400000>;
110};
111
112&pfc {
113	can0_pins: can0 {
114		groups = "can0_data_d";
115		function = "can0";
116	};
117
118	ether_pins: ether {
119		groups = "eth_mdio", "eth_rmii";
120		function = "eth";
121	};
122
123	hscif0_pins: hscif0 {
124		groups = "hscif0_data", "hscif0_ctrl";
125		function = "hscif0";
126	};
127
128	i2c1_pins: i2c1 {
129		groups = "i2c1_c";
130		function = "i2c1";
131	};
132
133	i2c3_pins: i2c3 {
134		groups = "i2c3";
135		function = "i2c3";
136	};
137
138	scif0_pins: scif0 {
139		groups = "scif0_data";
140		function = "scif0";
141	};
142
143	scif1_pins: scif1 {
144		groups = "scif1_data";
145		function = "scif1";
146	};
147
148	scifb1_pins: scifb1 {
149		groups = "scifb1_data";
150		function = "scifb1";
151	};
152
153	vin0_8bit_pins: vin0 {
154		groups = "vin0_data8", "vin0_clk", "vin0_sync";
155		function = "vin0";
156	};
157
158	vin1_8bit_pins: vin1 {
159		groups = "vin1_data8_b", "vin1_clk_b", "vin1_sync_b";
160		function = "vin1";
161	};
162
163	vin2_pins: vin2 {
164		groups = "vin2_g8", "vin2_clk";
165		function = "vin2";
166	};
167
168	vin3_pins: vin3 {
169		groups = "vin3_data8", "vin3_clk", "vin3_sync";
170		function = "vin3";
171	};
172};
173
174&qspi {
175	/* Pins shared with VIN2, keep status disabled */
176	status = "disabled";
177};
178
179&scif0 {
180	pinctrl-0 = <&scif0_pins>;
181	pinctrl-names = "default";
182	status = "okay";
183};
184
185&scif1 {
186	pinctrl-0 = <&scif1_pins>;
187	pinctrl-names = "default";
188	status = "okay";
189};
190
191&scifb1 {
192	pinctrl-0 = <&scifb1_pins>;
193	pinctrl-names = "default";
194	status = "okay";
195
196	rts-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
197	cts-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
198};
199
200/*
201 * Below configuration ties VINx endpoints to ov5640/ov7725 camera endpoints
202 *
203 * (un)comment the #include statements to change configuration
204 */
205
206/* 8bit CMOS Camera 1 (J13) */
207#define CAM_PARENT_I2C		i2c0
208#define MCLK_CAM		mclk_cam1
209#define CAM_EP			cam0ep
210#define VIN_EP			vin0ep
211#undef CAM_ENABLED
212#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi"
213//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi"
214
215#ifdef CAM_ENABLED
216&vin0 {
217	/*
218	 * Set SW2 switch on the SOM to 'ON'
219	 * Set SW1 switch on camera board to 'OFF' as we are using 8bit mode
220	 */
221	status = "okay";
222	pinctrl-0 = <&vin0_8bit_pins>;
223	pinctrl-names = "default";
224
225	port {
226		vin0ep: endpoint {
227			remote-endpoint = <&cam0ep>;
228			bus-width = <8>;
229			bus-type = <6>;
230		};
231	};
232};
233#endif /* CAM_ENABLED */
234
235#undef CAM_PARENT_I2C
236#undef MCLK_CAM
237#undef CAM_EP
238#undef VIN_EP
239
240/* 8bit CMOS Camera 2 (J14) */
241#define CAM_PARENT_I2C		i2c1
242#define MCLK_CAM		mclk_cam2
243#define CAM_EP			cam1ep
244#define VIN_EP			vin1ep
245#undef CAM_ENABLED
246#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi"
247//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi"
248
249#ifdef CAM_ENABLED
250&vin1 {
251	/* Set SW1 switch on the SOM to 'ON' */
252	status = "okay";
253	pinctrl-0 = <&vin1_8bit_pins>;
254	pinctrl-names = "default";
255
256	port {
257		vin1ep: endpoint {
258			remote-endpoint = <&cam1ep>;
259			bus-width = <8>;
260			bus-type = <6>;
261		};
262	};
263};
264
265#endif /* CAM_ENABLED */
266
267#undef CAM_PARENT_I2C
268#undef MCLK_CAM
269#undef CAM_EP
270#undef VIN_EP
271
272/* 8bit CMOS Camera 3 (J12) */
273#define CAM_PARENT_I2C		i2c2
274#define MCLK_CAM		mclk_cam3
275#define CAM_EP			cam2ep
276#define VIN_EP			vin2ep
277#undef CAM_ENABLED
278#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi"
279//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi"
280
281#ifdef CAM_ENABLED
282&vin2 {
283	status = "okay";
284	pinctrl-0 = <&vin2_pins>;
285	pinctrl-names = "default";
286
287	port {
288		vin2ep: endpoint {
289			remote-endpoint = <&cam2ep>;
290			bus-width = <8>;
291			data-shift = <8>;
292			bus-type = <6>;
293		};
294	};
295};
296#endif /* CAM_ENABLED */
297
298#undef CAM_PARENT_I2C
299#undef MCLK_CAM
300#undef CAM_EP
301#undef VIN_EP
302
303/* 8bit CMOS Camera 4 (J11) */
304#define CAM_PARENT_I2C		i2c3
305#define MCLK_CAM		mclk_cam4
306#define CAM_EP			cam3ep
307#define VIN_EP			vin3ep
308#undef CAM_ENABLED
309#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi"
310//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi"
311
312#ifdef CAM_ENABLED
313&vin3 {
314	status = "okay";
315	pinctrl-0 = <&vin3_pins>;
316	pinctrl-names = "default";
317
318	port {
319		vin3ep: endpoint {
320			remote-endpoint = <&cam3ep>;
321			bus-width = <8>;
322			bus-type = <6>;
323		};
324	};
325};
326#endif /* CAM_ENABLED */
327
328#undef CAM_PARENT_I2C
329#undef MCLK_CAM
330#undef CAM_EP
331#undef VIN_EP
332