1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car M2-N (R8A77930) SoC 4 * 5 * Copyright (C) 2014-2015 Renesas Electronics Corporation 6 */ 7 8#include <dt-bindings/clock/r8a7793-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/power/r8a7793-sysc.h> 12 13/ { 14 compatible = "renesas,r8a7793"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 i2c0 = &i2c0; 20 i2c1 = &i2c1; 21 i2c2 = &i2c2; 22 i2c3 = &i2c3; 23 i2c4 = &i2c4; 24 i2c5 = &i2c5; 25 i2c6 = &i2c6; 26 i2c7 = &i2c7; 27 i2c8 = &i2c8; 28 spi0 = &qspi; 29 }; 30 31 /* 32 * The external audio clocks are configured as 0 Hz fixed frequency 33 * clocks by default. 34 * Boards that provide audio clocks should override them. 35 */ 36 audio_clk_a: audio_clk_a { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <0>; 40 }; 41 audio_clk_b: audio_clk_b { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <0>; 45 }; 46 audio_clk_c: audio_clk_c { 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 clock-frequency = <0>; 50 }; 51 52 /* External CAN clock */ 53 can_clk: can { 54 compatible = "fixed-clock"; 55 #clock-cells = <0>; 56 /* This value must be overridden by the board. */ 57 clock-frequency = <0>; 58 }; 59 60 cpus { 61 #address-cells = <1>; 62 #size-cells = <0>; 63 64 cpu0: cpu@0 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a15"; 67 reg = <0>; 68 clock-frequency = <1500000000>; 69 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; 70 power-domains = <&sysc R8A7793_PD_CA15_CPU0>; 71 enable-method = "renesas,apmu"; 72 voltage-tolerance = <1>; /* 1% */ 73 clock-latency = <300000>; /* 300 us */ 74 75 /* kHz - uV - OPPs unknown yet */ 76 operating-points = <1500000 1000000>, 77 <1312500 1000000>, 78 <1125000 1000000>, 79 < 937500 1000000>, 80 < 750000 1000000>, 81 < 375000 1000000>; 82 next-level-cache = <&L2_CA15>; 83 }; 84 85 cpu1: cpu@1 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a15"; 88 reg = <1>; 89 clock-frequency = <1500000000>; 90 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; 91 power-domains = <&sysc R8A7793_PD_CA15_CPU1>; 92 enable-method = "renesas,apmu"; 93 voltage-tolerance = <1>; /* 1% */ 94 clock-latency = <300000>; /* 300 us */ 95 96 /* kHz - uV - OPPs unknown yet */ 97 operating-points = <1500000 1000000>, 98 <1312500 1000000>, 99 <1125000 1000000>, 100 < 937500 1000000>, 101 < 750000 1000000>, 102 < 375000 1000000>; 103 next-level-cache = <&L2_CA15>; 104 }; 105 106 L2_CA15: cache-controller-0 { 107 compatible = "cache"; 108 power-domains = <&sysc R8A7793_PD_CA15_SCU>; 109 cache-unified; 110 cache-level = <2>; 111 }; 112 }; 113 114 /* External root clock */ 115 extal_clk: extal { 116 compatible = "fixed-clock"; 117 #clock-cells = <0>; 118 /* This value must be overridden by the board. */ 119 clock-frequency = <0>; 120 }; 121 122 pmu { 123 compatible = "arm,cortex-a15-pmu"; 124 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 125 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 126 interrupt-affinity = <&cpu0>, <&cpu1>; 127 }; 128 129 /* External SCIF clock */ 130 scif_clk: scif { 131 compatible = "fixed-clock"; 132 #clock-cells = <0>; 133 /* This value must be overridden by the board. */ 134 clock-frequency = <0>; 135 }; 136 137 soc { 138 compatible = "simple-bus"; 139 interrupt-parent = <&gic>; 140 141 #address-cells = <2>; 142 #size-cells = <2>; 143 ranges; 144 145 rwdt: watchdog@e6020000 { 146 compatible = "renesas,r8a7793-wdt", 147 "renesas,rcar-gen2-wdt"; 148 reg = <0 0xe6020000 0 0x0c>; 149 clocks = <&cpg CPG_MOD 402>; 150 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 151 resets = <&cpg 402>; 152 status = "disabled"; 153 }; 154 155 gpio0: gpio@e6050000 { 156 compatible = "renesas,gpio-r8a7793", 157 "renesas,rcar-gen2-gpio"; 158 reg = <0 0xe6050000 0 0x50>; 159 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 160 #gpio-cells = <2>; 161 gpio-controller; 162 gpio-ranges = <&pfc 0 0 32>; 163 #interrupt-cells = <2>; 164 interrupt-controller; 165 clocks = <&cpg CPG_MOD 912>; 166 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 167 resets = <&cpg 912>; 168 }; 169 170 gpio1: gpio@e6051000 { 171 compatible = "renesas,gpio-r8a7793", 172 "renesas,rcar-gen2-gpio"; 173 reg = <0 0xe6051000 0 0x50>; 174 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 175 #gpio-cells = <2>; 176 gpio-controller; 177 gpio-ranges = <&pfc 0 32 26>; 178 #interrupt-cells = <2>; 179 interrupt-controller; 180 clocks = <&cpg CPG_MOD 911>; 181 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 182 resets = <&cpg 911>; 183 }; 184 185 gpio2: gpio@e6052000 { 186 compatible = "renesas,gpio-r8a7793", 187 "renesas,rcar-gen2-gpio"; 188 reg = <0 0xe6052000 0 0x50>; 189 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 190 #gpio-cells = <2>; 191 gpio-controller; 192 gpio-ranges = <&pfc 0 64 32>; 193 #interrupt-cells = <2>; 194 interrupt-controller; 195 clocks = <&cpg CPG_MOD 910>; 196 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 197 resets = <&cpg 910>; 198 }; 199 200 gpio3: gpio@e6053000 { 201 compatible = "renesas,gpio-r8a7793", 202 "renesas,rcar-gen2-gpio"; 203 reg = <0 0xe6053000 0 0x50>; 204 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 205 #gpio-cells = <2>; 206 gpio-controller; 207 gpio-ranges = <&pfc 0 96 32>; 208 #interrupt-cells = <2>; 209 interrupt-controller; 210 clocks = <&cpg CPG_MOD 909>; 211 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 212 resets = <&cpg 909>; 213 }; 214 215 gpio4: gpio@e6054000 { 216 compatible = "renesas,gpio-r8a7793", 217 "renesas,rcar-gen2-gpio"; 218 reg = <0 0xe6054000 0 0x50>; 219 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 220 #gpio-cells = <2>; 221 gpio-controller; 222 gpio-ranges = <&pfc 0 128 32>; 223 #interrupt-cells = <2>; 224 interrupt-controller; 225 clocks = <&cpg CPG_MOD 908>; 226 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 227 resets = <&cpg 908>; 228 }; 229 230 gpio5: gpio@e6055000 { 231 compatible = "renesas,gpio-r8a7793", 232 "renesas,rcar-gen2-gpio"; 233 reg = <0 0xe6055000 0 0x50>; 234 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 235 #gpio-cells = <2>; 236 gpio-controller; 237 gpio-ranges = <&pfc 0 160 32>; 238 #interrupt-cells = <2>; 239 interrupt-controller; 240 clocks = <&cpg CPG_MOD 907>; 241 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 242 resets = <&cpg 907>; 243 }; 244 245 gpio6: gpio@e6055400 { 246 compatible = "renesas,gpio-r8a7793", 247 "renesas,rcar-gen2-gpio"; 248 reg = <0 0xe6055400 0 0x50>; 249 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 250 #gpio-cells = <2>; 251 gpio-controller; 252 gpio-ranges = <&pfc 0 192 32>; 253 #interrupt-cells = <2>; 254 interrupt-controller; 255 clocks = <&cpg CPG_MOD 905>; 256 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 257 resets = <&cpg 905>; 258 }; 259 260 gpio7: gpio@e6055800 { 261 compatible = "renesas,gpio-r8a7793", 262 "renesas,rcar-gen2-gpio"; 263 reg = <0 0xe6055800 0 0x50>; 264 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 265 #gpio-cells = <2>; 266 gpio-controller; 267 gpio-ranges = <&pfc 0 224 26>; 268 #interrupt-cells = <2>; 269 interrupt-controller; 270 clocks = <&cpg CPG_MOD 904>; 271 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 272 resets = <&cpg 904>; 273 }; 274 275 pfc: pinctrl@e6060000 { 276 compatible = "renesas,pfc-r8a7793"; 277 reg = <0 0xe6060000 0 0x250>; 278 }; 279 280 /* Special CPG clocks */ 281 cpg: clock-controller@e6150000 { 282 compatible = "renesas,r8a7793-cpg-mssr"; 283 reg = <0 0xe6150000 0 0x1000>; 284 clocks = <&extal_clk>, <&usb_extal_clk>; 285 clock-names = "extal", "usb_extal"; 286 #clock-cells = <2>; 287 #power-domain-cells = <0>; 288 #reset-cells = <1>; 289 }; 290 291 apmu@e6152000 { 292 compatible = "renesas,r8a7793-apmu", "renesas,apmu"; 293 reg = <0 0xe6152000 0 0x188>; 294 cpus = <&cpu0>, <&cpu1>; 295 }; 296 297 rst: reset-controller@e6160000 { 298 compatible = "renesas,r8a7793-rst"; 299 reg = <0 0xe6160000 0 0x0100>; 300 }; 301 302 sysc: system-controller@e6180000 { 303 compatible = "renesas,r8a7793-sysc"; 304 reg = <0 0xe6180000 0 0x0200>; 305 #power-domain-cells = <1>; 306 }; 307 308 irqc0: interrupt-controller@e61c0000 { 309 compatible = "renesas,irqc-r8a7793", "renesas,irqc"; 310 #interrupt-cells = <2>; 311 interrupt-controller; 312 reg = <0 0xe61c0000 0 0x200>; 313 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&cpg CPG_MOD 407>; 324 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 325 resets = <&cpg 407>; 326 }; 327 328 thermal: thermal@e61f0000 { 329 compatible = "renesas,thermal-r8a7793", 330 "renesas,rcar-gen2-thermal", 331 "renesas,rcar-thermal"; 332 reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; 333 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&cpg CPG_MOD 522>; 335 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 336 resets = <&cpg 522>; 337 #thermal-sensor-cells = <0>; 338 }; 339 340 ipmmu_sy0: iommu@e6280000 { 341 compatible = "renesas,ipmmu-r8a7793", 342 "renesas,ipmmu-vmsa"; 343 reg = <0 0xe6280000 0 0x1000>; 344 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 346 #iommu-cells = <1>; 347 status = "disabled"; 348 }; 349 350 ipmmu_sy1: iommu@e6290000 { 351 compatible = "renesas,ipmmu-r8a7793", 352 "renesas,ipmmu-vmsa"; 353 reg = <0 0xe6290000 0 0x1000>; 354 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 355 #iommu-cells = <1>; 356 status = "disabled"; 357 }; 358 359 ipmmu_ds: iommu@e6740000 { 360 compatible = "renesas,ipmmu-r8a7793", 361 "renesas,ipmmu-vmsa"; 362 reg = <0 0xe6740000 0 0x1000>; 363 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 365 #iommu-cells = <1>; 366 status = "disabled"; 367 }; 368 369 ipmmu_mp: iommu@ec680000 { 370 compatible = "renesas,ipmmu-r8a7793", 371 "renesas,ipmmu-vmsa"; 372 reg = <0 0xec680000 0 0x1000>; 373 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 374 #iommu-cells = <1>; 375 status = "disabled"; 376 }; 377 378 ipmmu_mx: iommu@fe951000 { 379 compatible = "renesas,ipmmu-r8a7793", 380 "renesas,ipmmu-vmsa"; 381 reg = <0 0xfe951000 0 0x1000>; 382 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 384 #iommu-cells = <1>; 385 status = "disabled"; 386 }; 387 388 ipmmu_rt: iommu@ffc80000 { 389 compatible = "renesas,ipmmu-r8a7793", 390 "renesas,ipmmu-vmsa"; 391 reg = <0 0xffc80000 0 0x1000>; 392 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 393 #iommu-cells = <1>; 394 status = "disabled"; 395 }; 396 397 ipmmu_gp: iommu@e62a0000 { 398 compatible = "renesas,ipmmu-r8a7793", 399 "renesas,ipmmu-vmsa"; 400 reg = <0 0xe62a0000 0 0x1000>; 401 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 403 #iommu-cells = <1>; 404 status = "disabled"; 405 }; 406 407 icram0: sram@e63a0000 { 408 compatible = "mmio-sram"; 409 reg = <0 0xe63a0000 0 0x12000>; 410 #address-cells = <1>; 411 #size-cells = <1>; 412 ranges = <0 0 0xe63a0000 0x12000>; 413 }; 414 415 icram1: sram@e63c0000 { 416 compatible = "mmio-sram"; 417 reg = <0 0xe63c0000 0 0x1000>; 418 #address-cells = <1>; 419 #size-cells = <1>; 420 ranges = <0 0 0xe63c0000 0x1000>; 421 422 smp-sram@0 { 423 compatible = "renesas,smp-sram"; 424 reg = <0 0x100>; 425 }; 426 }; 427 428 /* The memory map in the User's Manual maps the cores to 429 * bus numbers 430 */ 431 i2c0: i2c@e6508000 { 432 #address-cells = <1>; 433 #size-cells = <0>; 434 compatible = "renesas,i2c-r8a7793", 435 "renesas,rcar-gen2-i2c"; 436 reg = <0 0xe6508000 0 0x40>; 437 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&cpg CPG_MOD 931>; 439 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 440 resets = <&cpg 931>; 441 i2c-scl-internal-delay-ns = <6>; 442 status = "disabled"; 443 }; 444 445 i2c1: i2c@e6518000 { 446 #address-cells = <1>; 447 #size-cells = <0>; 448 compatible = "renesas,i2c-r8a7793", 449 "renesas,rcar-gen2-i2c"; 450 reg = <0 0xe6518000 0 0x40>; 451 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&cpg CPG_MOD 930>; 453 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 454 resets = <&cpg 930>; 455 i2c-scl-internal-delay-ns = <6>; 456 status = "disabled"; 457 }; 458 459 i2c2: i2c@e6530000 { 460 #address-cells = <1>; 461 #size-cells = <0>; 462 compatible = "renesas,i2c-r8a7793", 463 "renesas,rcar-gen2-i2c"; 464 reg = <0 0xe6530000 0 0x40>; 465 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&cpg CPG_MOD 929>; 467 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 468 resets = <&cpg 929>; 469 i2c-scl-internal-delay-ns = <6>; 470 status = "disabled"; 471 }; 472 473 i2c3: i2c@e6540000 { 474 #address-cells = <1>; 475 #size-cells = <0>; 476 compatible = "renesas,i2c-r8a7793", 477 "renesas,rcar-gen2-i2c"; 478 reg = <0 0xe6540000 0 0x40>; 479 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&cpg CPG_MOD 928>; 481 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 482 resets = <&cpg 928>; 483 i2c-scl-internal-delay-ns = <6>; 484 status = "disabled"; 485 }; 486 487 i2c4: i2c@e6520000 { 488 #address-cells = <1>; 489 #size-cells = <0>; 490 compatible = "renesas,i2c-r8a7793", 491 "renesas,rcar-gen2-i2c"; 492 reg = <0 0xe6520000 0 0x40>; 493 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&cpg CPG_MOD 927>; 495 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 496 resets = <&cpg 927>; 497 i2c-scl-internal-delay-ns = <6>; 498 status = "disabled"; 499 }; 500 501 i2c5: i2c@e6528000 { 502 /* doesn't need pinmux */ 503 #address-cells = <1>; 504 #size-cells = <0>; 505 compatible = "renesas,i2c-r8a7793", 506 "renesas,rcar-gen2-i2c"; 507 reg = <0 0xe6528000 0 0x40>; 508 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&cpg CPG_MOD 925>; 510 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 511 resets = <&cpg 925>; 512 i2c-scl-internal-delay-ns = <110>; 513 status = "disabled"; 514 }; 515 516 i2c6: i2c@e60b0000 { 517 /* doesn't need pinmux */ 518 #address-cells = <1>; 519 #size-cells = <0>; 520 compatible = "renesas,iic-r8a7793", 521 "renesas,rcar-gen2-iic", 522 "renesas,rmobile-iic"; 523 reg = <0 0xe60b0000 0 0x425>; 524 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&cpg CPG_MOD 926>; 526 dmas = <&dmac0 0x77>, <&dmac0 0x78>, 527 <&dmac1 0x77>, <&dmac1 0x78>; 528 dma-names = "tx", "rx", "tx", "rx"; 529 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 530 resets = <&cpg 926>; 531 status = "disabled"; 532 }; 533 534 i2c7: i2c@e6500000 { 535 #address-cells = <1>; 536 #size-cells = <0>; 537 compatible = "renesas,iic-r8a7793", 538 "renesas,rcar-gen2-iic", 539 "renesas,rmobile-iic"; 540 reg = <0 0xe6500000 0 0x425>; 541 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&cpg CPG_MOD 318>; 543 dmas = <&dmac0 0x61>, <&dmac0 0x62>, 544 <&dmac1 0x61>, <&dmac1 0x62>; 545 dma-names = "tx", "rx", "tx", "rx"; 546 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 547 resets = <&cpg 318>; 548 status = "disabled"; 549 }; 550 551 i2c8: i2c@e6510000 { 552 #address-cells = <1>; 553 #size-cells = <0>; 554 compatible = "renesas,iic-r8a7793", 555 "renesas,rcar-gen2-iic", 556 "renesas,rmobile-iic"; 557 reg = <0 0xe6510000 0 0x425>; 558 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&cpg CPG_MOD 323>; 560 dmas = <&dmac0 0x65>, <&dmac0 0x66>, 561 <&dmac1 0x65>, <&dmac1 0x66>; 562 dma-names = "tx", "rx", "tx", "rx"; 563 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 564 resets = <&cpg 323>; 565 status = "disabled"; 566 }; 567 568 dmac0: dma-controller@e6700000 { 569 compatible = "renesas,dmac-r8a7793", 570 "renesas,rcar-dmac"; 571 reg = <0 0xe6700000 0 0x20000>; 572 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 588 interrupt-names = "error", 589 "ch0", "ch1", "ch2", "ch3", 590 "ch4", "ch5", "ch6", "ch7", 591 "ch8", "ch9", "ch10", "ch11", 592 "ch12", "ch13", "ch14"; 593 clocks = <&cpg CPG_MOD 219>; 594 clock-names = "fck"; 595 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 596 resets = <&cpg 219>; 597 #dma-cells = <1>; 598 dma-channels = <15>; 599 }; 600 601 dmac1: dma-controller@e6720000 { 602 compatible = "renesas,dmac-r8a7793", 603 "renesas,rcar-dmac"; 604 reg = <0 0xe6720000 0 0x20000>; 605 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 621 interrupt-names = "error", 622 "ch0", "ch1", "ch2", "ch3", 623 "ch4", "ch5", "ch6", "ch7", 624 "ch8", "ch9", "ch10", "ch11", 625 "ch12", "ch13", "ch14"; 626 clocks = <&cpg CPG_MOD 218>; 627 clock-names = "fck"; 628 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 629 resets = <&cpg 218>; 630 #dma-cells = <1>; 631 dma-channels = <15>; 632 }; 633 634 qspi: spi@e6b10000 { 635 compatible = "renesas,qspi-r8a7793", "renesas,qspi"; 636 reg = <0 0xe6b10000 0 0x2c>; 637 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&cpg CPG_MOD 917>; 639 dmas = <&dmac0 0x17>, <&dmac0 0x18>, 640 <&dmac1 0x17>, <&dmac1 0x18>; 641 dma-names = "tx", "rx", "tx", "rx"; 642 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 643 resets = <&cpg 917>; 644 num-cs = <1>; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 status = "disabled"; 648 }; 649 650 scifa0: serial@e6c40000 { 651 compatible = "renesas,scifa-r8a7793", 652 "renesas,rcar-gen2-scifa", "renesas,scifa"; 653 reg = <0 0xe6c40000 0 64>; 654 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 655 clocks = <&cpg CPG_MOD 204>; 656 clock-names = "fck"; 657 dmas = <&dmac0 0x21>, <&dmac0 0x22>, 658 <&dmac1 0x21>, <&dmac1 0x22>; 659 dma-names = "tx", "rx", "tx", "rx"; 660 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 661 resets = <&cpg 204>; 662 status = "disabled"; 663 }; 664 665 scifa1: serial@e6c50000 { 666 compatible = "renesas,scifa-r8a7793", 667 "renesas,rcar-gen2-scifa", "renesas,scifa"; 668 reg = <0 0xe6c50000 0 64>; 669 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 670 clocks = <&cpg CPG_MOD 203>; 671 clock-names = "fck"; 672 dmas = <&dmac0 0x25>, <&dmac0 0x26>, 673 <&dmac1 0x25>, <&dmac1 0x26>; 674 dma-names = "tx", "rx", "tx", "rx"; 675 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 676 resets = <&cpg 203>; 677 status = "disabled"; 678 }; 679 680 scifa2: serial@e6c60000 { 681 compatible = "renesas,scifa-r8a7793", 682 "renesas,rcar-gen2-scifa", "renesas,scifa"; 683 reg = <0 0xe6c60000 0 64>; 684 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&cpg CPG_MOD 202>; 686 clock-names = "fck"; 687 dmas = <&dmac0 0x27>, <&dmac0 0x28>, 688 <&dmac1 0x27>, <&dmac1 0x28>; 689 dma-names = "tx", "rx", "tx", "rx"; 690 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 691 resets = <&cpg 202>; 692 status = "disabled"; 693 }; 694 695 scifa3: serial@e6c70000 { 696 compatible = "renesas,scifa-r8a7793", 697 "renesas,rcar-gen2-scifa", "renesas,scifa"; 698 reg = <0 0xe6c70000 0 64>; 699 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&cpg CPG_MOD 1106>; 701 clock-names = "fck"; 702 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, 703 <&dmac1 0x1b>, <&dmac1 0x1c>; 704 dma-names = "tx", "rx", "tx", "rx"; 705 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 706 resets = <&cpg 1106>; 707 status = "disabled"; 708 }; 709 710 scifa4: serial@e6c78000 { 711 compatible = "renesas,scifa-r8a7793", 712 "renesas,rcar-gen2-scifa", "renesas,scifa"; 713 reg = <0 0xe6c78000 0 64>; 714 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 715 clocks = <&cpg CPG_MOD 1107>; 716 clock-names = "fck"; 717 dmas = <&dmac0 0x1f>, <&dmac0 0x20>, 718 <&dmac1 0x1f>, <&dmac1 0x20>; 719 dma-names = "tx", "rx", "tx", "rx"; 720 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 721 resets = <&cpg 1107>; 722 status = "disabled"; 723 }; 724 725 scifa5: serial@e6c80000 { 726 compatible = "renesas,scifa-r8a7793", 727 "renesas,rcar-gen2-scifa", "renesas,scifa"; 728 reg = <0 0xe6c80000 0 64>; 729 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&cpg CPG_MOD 1108>; 731 clock-names = "fck"; 732 dmas = <&dmac0 0x23>, <&dmac0 0x24>, 733 <&dmac1 0x23>, <&dmac1 0x24>; 734 dma-names = "tx", "rx", "tx", "rx"; 735 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 736 resets = <&cpg 1108>; 737 status = "disabled"; 738 }; 739 740 scifb0: serial@e6c20000 { 741 compatible = "renesas,scifb-r8a7793", 742 "renesas,rcar-gen2-scifb", "renesas,scifb"; 743 reg = <0 0xe6c20000 0 0x100>; 744 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 745 clocks = <&cpg CPG_MOD 206>; 746 clock-names = "fck"; 747 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, 748 <&dmac1 0x3d>, <&dmac1 0x3e>; 749 dma-names = "tx", "rx", "tx", "rx"; 750 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 751 resets = <&cpg 206>; 752 status = "disabled"; 753 }; 754 755 scifb1: serial@e6c30000 { 756 compatible = "renesas,scifb-r8a7793", 757 "renesas,rcar-gen2-scifb", "renesas,scifb"; 758 reg = <0 0xe6c30000 0 0x100>; 759 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 760 clocks = <&cpg CPG_MOD 207>; 761 clock-names = "fck"; 762 dmas = <&dmac0 0x19>, <&dmac0 0x1a>, 763 <&dmac1 0x19>, <&dmac1 0x1a>; 764 dma-names = "tx", "rx", "tx", "rx"; 765 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 766 resets = <&cpg 207>; 767 status = "disabled"; 768 }; 769 770 scifb2: serial@e6ce0000 { 771 compatible = "renesas,scifb-r8a7793", 772 "renesas,rcar-gen2-scifb", "renesas,scifb"; 773 reg = <0 0xe6ce0000 0 0x100>; 774 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&cpg CPG_MOD 216>; 776 clock-names = "fck"; 777 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, 778 <&dmac1 0x1d>, <&dmac1 0x1e>; 779 dma-names = "tx", "rx", "tx", "rx"; 780 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 781 resets = <&cpg 216>; 782 status = "disabled"; 783 }; 784 785 scif0: serial@e6e60000 { 786 compatible = "renesas,scif-r8a7793", 787 "renesas,rcar-gen2-scif", "renesas,scif"; 788 reg = <0 0xe6e60000 0 64>; 789 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 790 clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 791 <&scif_clk>; 792 clock-names = "fck", "brg_int", "scif_clk"; 793 dmas = <&dmac0 0x29>, <&dmac0 0x2a>, 794 <&dmac1 0x29>, <&dmac1 0x2a>; 795 dma-names = "tx", "rx", "tx", "rx"; 796 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 797 resets = <&cpg 721>; 798 status = "disabled"; 799 }; 800 801 scif1: serial@e6e68000 { 802 compatible = "renesas,scif-r8a7793", 803 "renesas,rcar-gen2-scif", "renesas,scif"; 804 reg = <0 0xe6e68000 0 64>; 805 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 806 clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 807 <&scif_clk>; 808 clock-names = "fck", "brg_int", "scif_clk"; 809 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, 810 <&dmac1 0x2d>, <&dmac1 0x2e>; 811 dma-names = "tx", "rx", "tx", "rx"; 812 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 813 resets = <&cpg 720>; 814 status = "disabled"; 815 }; 816 817 scif2: serial@e6e58000 { 818 compatible = "renesas,scif-r8a7793", 819 "renesas,rcar-gen2-scif", "renesas,scif"; 820 reg = <0 0xe6e58000 0 64>; 821 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 822 clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 823 <&scif_clk>; 824 clock-names = "fck", "brg_int", "scif_clk"; 825 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, 826 <&dmac1 0x2b>, <&dmac1 0x2c>; 827 dma-names = "tx", "rx", "tx", "rx"; 828 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 829 resets = <&cpg 719>; 830 status = "disabled"; 831 }; 832 833 scif3: serial@e6ea8000 { 834 compatible = "renesas,scif-r8a7793", 835 "renesas,rcar-gen2-scif", "renesas,scif"; 836 reg = <0 0xe6ea8000 0 64>; 837 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 838 clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 839 <&scif_clk>; 840 clock-names = "fck", "brg_int", "scif_clk"; 841 dmas = <&dmac0 0x2f>, <&dmac0 0x30>, 842 <&dmac1 0x2f>, <&dmac1 0x30>; 843 dma-names = "tx", "rx", "tx", "rx"; 844 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 845 resets = <&cpg 718>; 846 status = "disabled"; 847 }; 848 849 scif4: serial@e6ee0000 { 850 compatible = "renesas,scif-r8a7793", 851 "renesas,rcar-gen2-scif", "renesas,scif"; 852 reg = <0 0xe6ee0000 0 64>; 853 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 855 <&scif_clk>; 856 clock-names = "fck", "brg_int", "scif_clk"; 857 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, 858 <&dmac1 0xfb>, <&dmac1 0xfc>; 859 dma-names = "tx", "rx", "tx", "rx"; 860 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 861 resets = <&cpg 715>; 862 status = "disabled"; 863 }; 864 865 scif5: serial@e6ee8000 { 866 compatible = "renesas,scif-r8a7793", 867 "renesas,rcar-gen2-scif", "renesas,scif"; 868 reg = <0 0xe6ee8000 0 64>; 869 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 871 <&scif_clk>; 872 clock-names = "fck", "brg_int", "scif_clk"; 873 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, 874 <&dmac1 0xfd>, <&dmac1 0xfe>; 875 dma-names = "tx", "rx", "tx", "rx"; 876 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 877 resets = <&cpg 714>; 878 status = "disabled"; 879 }; 880 881 hscif0: serial@e62c0000 { 882 compatible = "renesas,hscif-r8a7793", 883 "renesas,rcar-gen2-hscif", "renesas,hscif"; 884 reg = <0 0xe62c0000 0 96>; 885 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 886 clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 887 <&scif_clk>; 888 clock-names = "fck", "brg_int", "scif_clk"; 889 dmas = <&dmac0 0x39>, <&dmac0 0x3a>, 890 <&dmac1 0x39>, <&dmac1 0x3a>; 891 dma-names = "tx", "rx", "tx", "rx"; 892 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 893 resets = <&cpg 717>; 894 status = "disabled"; 895 }; 896 897 hscif1: serial@e62c8000 { 898 compatible = "renesas,hscif-r8a7793", 899 "renesas,rcar-gen2-hscif", "renesas,hscif"; 900 reg = <0 0xe62c8000 0 96>; 901 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 903 <&scif_clk>; 904 clock-names = "fck", "brg_int", "scif_clk"; 905 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, 906 <&dmac1 0x4d>, <&dmac1 0x4e>; 907 dma-names = "tx", "rx", "tx", "rx"; 908 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 909 resets = <&cpg 716>; 910 status = "disabled"; 911 }; 912 913 hscif2: serial@e62d0000 { 914 compatible = "renesas,hscif-r8a7793", 915 "renesas,rcar-gen2-hscif", "renesas,hscif"; 916 reg = <0 0xe62d0000 0 96>; 917 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 919 <&scif_clk>; 920 clock-names = "fck", "brg_int", "scif_clk"; 921 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, 922 <&dmac1 0x3b>, <&dmac1 0x3c>; 923 dma-names = "tx", "rx", "tx", "rx"; 924 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 925 resets = <&cpg 713>; 926 status = "disabled"; 927 }; 928 929 can0: can@e6e80000 { 930 compatible = "renesas,can-r8a7793", 931 "renesas,rcar-gen2-can"; 932 reg = <0 0xe6e80000 0 0x1000>; 933 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 934 clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, 935 <&can_clk>; 936 clock-names = "clkp1", "clkp2", "can_clk"; 937 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 938 resets = <&cpg 916>; 939 status = "disabled"; 940 }; 941 942 can1: can@e6e88000 { 943 compatible = "renesas,can-r8a7793", 944 "renesas,rcar-gen2-can"; 945 reg = <0 0xe6e88000 0 0x1000>; 946 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 947 clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, 948 <&can_clk>; 949 clock-names = "clkp1", "clkp2", "can_clk"; 950 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 951 resets = <&cpg 915>; 952 status = "disabled"; 953 }; 954 955 vin0: video@e6ef0000 { 956 compatible = "renesas,vin-r8a7793", 957 "renesas,rcar-gen2-vin"; 958 reg = <0 0xe6ef0000 0 0x1000>; 959 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&cpg CPG_MOD 811>; 961 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 962 resets = <&cpg 811>; 963 status = "disabled"; 964 }; 965 966 vin1: video@e6ef1000 { 967 compatible = "renesas,vin-r8a7793", 968 "renesas,rcar-gen2-vin"; 969 reg = <0 0xe6ef1000 0 0x1000>; 970 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 971 clocks = <&cpg CPG_MOD 810>; 972 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 973 resets = <&cpg 810>; 974 status = "disabled"; 975 }; 976 977 vin2: video@e6ef2000 { 978 compatible = "renesas,vin-r8a7793", 979 "renesas,rcar-gen2-vin"; 980 reg = <0 0xe6ef2000 0 0x1000>; 981 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&cpg CPG_MOD 809>; 983 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 984 resets = <&cpg 809>; 985 status = "disabled"; 986 }; 987 988 rcar_sound: sound@ec500000 { 989 /* 990 * #sound-dai-cells is required 991 * 992 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 993 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 994 */ 995 compatible = "renesas,rcar_sound-r8a7793", 996 "renesas,rcar_sound-gen2"; 997 reg = <0 0xec500000 0 0x1000>, /* SCU */ 998 <0 0xec5a0000 0 0x100>, /* ADG */ 999 <0 0xec540000 0 0x1000>, /* SSIU */ 1000 <0 0xec541000 0 0x280>, /* SSI */ 1001 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 1002 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1003 1004 clocks = <&cpg CPG_MOD 1005>, 1005 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1006 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1007 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1008 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1009 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1010 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1011 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1012 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1013 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1014 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1015 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1016 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, 1017 <&cpg CPG_CORE R8A7793_CLK_M2>; 1018 clock-names = "ssi-all", 1019 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1020 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1021 "ssi.1", "ssi.0", 1022 "src.9", "src.8", "src.7", "src.6", 1023 "src.5", "src.4", "src.3", "src.2", 1024 "src.1", "src.0", 1025 "dvc.0", "dvc.1", 1026 "clk_a", "clk_b", "clk_c", "clk_i"; 1027 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1028 resets = <&cpg 1005>, 1029 <&cpg 1006>, <&cpg 1007>, 1030 <&cpg 1008>, <&cpg 1009>, 1031 <&cpg 1010>, <&cpg 1011>, 1032 <&cpg 1012>, <&cpg 1013>, 1033 <&cpg 1014>, <&cpg 1015>; 1034 reset-names = "ssi-all", 1035 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1036 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1037 "ssi.1", "ssi.0"; 1038 1039 status = "disabled"; 1040 1041 rcar_sound,dvc { 1042 dvc0: dvc-0 { 1043 dmas = <&audma1 0xbc>; 1044 dma-names = "tx"; 1045 }; 1046 dvc1: dvc-1 { 1047 dmas = <&audma1 0xbe>; 1048 dma-names = "tx"; 1049 }; 1050 }; 1051 1052 rcar_sound,src { 1053 src0: src-0 { 1054 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1055 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1056 dma-names = "rx", "tx"; 1057 }; 1058 src1: src-1 { 1059 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1060 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1061 dma-names = "rx", "tx"; 1062 }; 1063 src2: src-2 { 1064 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1065 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1066 dma-names = "rx", "tx"; 1067 }; 1068 src3: src-3 { 1069 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1070 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1071 dma-names = "rx", "tx"; 1072 }; 1073 src4: src-4 { 1074 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1075 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1076 dma-names = "rx", "tx"; 1077 }; 1078 src5: src-5 { 1079 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1080 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1081 dma-names = "rx", "tx"; 1082 }; 1083 src6: src-6 { 1084 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1085 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1086 dma-names = "rx", "tx"; 1087 }; 1088 src7: src-7 { 1089 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1090 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1091 dma-names = "rx", "tx"; 1092 }; 1093 src8: src-8 { 1094 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1095 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1096 dma-names = "rx", "tx"; 1097 }; 1098 src9: src-9 { 1099 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1100 dmas = <&audma0 0x97>, <&audma1 0xba>; 1101 dma-names = "rx", "tx"; 1102 }; 1103 }; 1104 1105 rcar_sound,ssi { 1106 ssi0: ssi-0 { 1107 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1108 dmas = <&audma0 0x01>, <&audma1 0x02>, 1109 <&audma0 0x15>, <&audma1 0x16>; 1110 dma-names = "rx", "tx", "rxu", "txu"; 1111 }; 1112 ssi1: ssi-1 { 1113 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1114 dmas = <&audma0 0x03>, <&audma1 0x04>, 1115 <&audma0 0x49>, <&audma1 0x4a>; 1116 dma-names = "rx", "tx", "rxu", "txu"; 1117 }; 1118 ssi2: ssi-2 { 1119 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1120 dmas = <&audma0 0x05>, <&audma1 0x06>, 1121 <&audma0 0x63>, <&audma1 0x64>; 1122 dma-names = "rx", "tx", "rxu", "txu"; 1123 }; 1124 ssi3: ssi-3 { 1125 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1126 dmas = <&audma0 0x07>, <&audma1 0x08>, 1127 <&audma0 0x6f>, <&audma1 0x70>; 1128 dma-names = "rx", "tx", "rxu", "txu"; 1129 }; 1130 ssi4: ssi-4 { 1131 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1132 dmas = <&audma0 0x09>, <&audma1 0x0a>, 1133 <&audma0 0x71>, <&audma1 0x72>; 1134 dma-names = "rx", "tx", "rxu", "txu"; 1135 }; 1136 ssi5: ssi-5 { 1137 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1138 dmas = <&audma0 0x0b>, <&audma1 0x0c>, 1139 <&audma0 0x73>, <&audma1 0x74>; 1140 dma-names = "rx", "tx", "rxu", "txu"; 1141 }; 1142 ssi6: ssi-6 { 1143 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1144 dmas = <&audma0 0x0d>, <&audma1 0x0e>, 1145 <&audma0 0x75>, <&audma1 0x76>; 1146 dma-names = "rx", "tx", "rxu", "txu"; 1147 }; 1148 ssi7: ssi-7 { 1149 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1150 dmas = <&audma0 0x0f>, <&audma1 0x10>, 1151 <&audma0 0x79>, <&audma1 0x7a>; 1152 dma-names = "rx", "tx", "rxu", "txu"; 1153 }; 1154 ssi8: ssi-8 { 1155 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1156 dmas = <&audma0 0x11>, <&audma1 0x12>, 1157 <&audma0 0x7b>, <&audma1 0x7c>; 1158 dma-names = "rx", "tx", "rxu", "txu"; 1159 }; 1160 ssi9: ssi-9 { 1161 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1162 dmas = <&audma0 0x13>, <&audma1 0x14>, 1163 <&audma0 0x7d>, <&audma1 0x7e>; 1164 dma-names = "rx", "tx", "rxu", "txu"; 1165 }; 1166 }; 1167 }; 1168 1169 audma0: dma-controller@ec700000 { 1170 compatible = "renesas,dmac-r8a7793", 1171 "renesas,rcar-dmac"; 1172 reg = <0 0xec700000 0 0x10000>; 1173 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1187 interrupt-names = "error", 1188 "ch0", "ch1", "ch2", "ch3", 1189 "ch4", "ch5", "ch6", "ch7", 1190 "ch8", "ch9", "ch10", "ch11", 1191 "ch12"; 1192 clocks = <&cpg CPG_MOD 502>; 1193 clock-names = "fck"; 1194 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1195 resets = <&cpg 502>; 1196 #dma-cells = <1>; 1197 dma-channels = <13>; 1198 }; 1199 1200 audma1: dma-controller@ec720000 { 1201 compatible = "renesas,dmac-r8a7793", 1202 "renesas,rcar-dmac"; 1203 reg = <0 0xec720000 0 0x10000>; 1204 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 1218 interrupt-names = "error", 1219 "ch0", "ch1", "ch2", "ch3", 1220 "ch4", "ch5", "ch6", "ch7", 1221 "ch8", "ch9", "ch10", "ch11", 1222 "ch12"; 1223 clocks = <&cpg CPG_MOD 501>; 1224 clock-names = "fck"; 1225 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1226 resets = <&cpg 501>; 1227 #dma-cells = <1>; 1228 dma-channels = <13>; 1229 }; 1230 1231 sdhi0: mmc@ee100000 { 1232 compatible = "renesas,sdhi-r8a7793", 1233 "renesas,rcar-gen2-sdhi"; 1234 reg = <0 0xee100000 0 0x328>; 1235 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1236 clocks = <&cpg CPG_MOD 314>; 1237 dmas = <&dmac0 0xcd>, <&dmac0 0xce>, 1238 <&dmac1 0xcd>, <&dmac1 0xce>; 1239 dma-names = "tx", "rx", "tx", "rx"; 1240 max-frequency = <195000000>; 1241 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1242 resets = <&cpg 314>; 1243 status = "disabled"; 1244 }; 1245 1246 sdhi1: mmc@ee140000 { 1247 compatible = "renesas,sdhi-r8a7793", 1248 "renesas,rcar-gen2-sdhi"; 1249 reg = <0 0xee140000 0 0x100>; 1250 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1251 clocks = <&cpg CPG_MOD 312>; 1252 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, 1253 <&dmac1 0xc1>, <&dmac1 0xc2>; 1254 dma-names = "tx", "rx", "tx", "rx"; 1255 max-frequency = <97500000>; 1256 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1257 resets = <&cpg 312>; 1258 status = "disabled"; 1259 }; 1260 1261 sdhi2: mmc@ee160000 { 1262 compatible = "renesas,sdhi-r8a7793", 1263 "renesas,rcar-gen2-sdhi"; 1264 reg = <0 0xee160000 0 0x100>; 1265 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1266 clocks = <&cpg CPG_MOD 311>; 1267 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, 1268 <&dmac1 0xd3>, <&dmac1 0xd4>; 1269 dma-names = "tx", "rx", "tx", "rx"; 1270 max-frequency = <97500000>; 1271 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1272 resets = <&cpg 311>; 1273 status = "disabled"; 1274 }; 1275 1276 mmcif0: mmc@ee200000 { 1277 compatible = "renesas,mmcif-r8a7793", 1278 "renesas,sh-mmcif"; 1279 reg = <0 0xee200000 0 0x80>; 1280 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1281 clocks = <&cpg CPG_MOD 315>; 1282 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, 1283 <&dmac1 0xd1>, <&dmac1 0xd2>; 1284 dma-names = "tx", "rx", "tx", "rx"; 1285 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1286 resets = <&cpg 315>; 1287 reg-io-width = <4>; 1288 status = "disabled"; 1289 max-frequency = <97500000>; 1290 }; 1291 1292 ether: ethernet@ee700000 { 1293 compatible = "renesas,ether-r8a7793", 1294 "renesas,rcar-gen2-ether"; 1295 reg = <0 0xee700000 0 0x400>; 1296 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1297 clocks = <&cpg CPG_MOD 813>; 1298 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1299 resets = <&cpg 813>; 1300 phy-mode = "rmii"; 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 status = "disabled"; 1304 }; 1305 1306 gic: interrupt-controller@f1001000 { 1307 compatible = "arm,gic-400"; 1308 #interrupt-cells = <3>; 1309 #address-cells = <0>; 1310 interrupt-controller; 1311 reg = <0 0xf1001000 0 0x1000>, 1312 <0 0xf1002000 0 0x2000>, 1313 <0 0xf1004000 0 0x2000>, 1314 <0 0xf1006000 0 0x2000>; 1315 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 1316 clocks = <&cpg CPG_MOD 408>; 1317 clock-names = "clk"; 1318 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1319 resets = <&cpg 408>; 1320 }; 1321 1322 fdp1@fe940000 { 1323 compatible = "renesas,fdp1"; 1324 reg = <0 0xfe940000 0 0x2400>; 1325 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 1326 clocks = <&cpg CPG_MOD 119>; 1327 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1328 resets = <&cpg 119>; 1329 }; 1330 1331 fdp1@fe944000 { 1332 compatible = "renesas,fdp1"; 1333 reg = <0 0xfe944000 0 0x2400>; 1334 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1335 clocks = <&cpg CPG_MOD 118>; 1336 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1337 resets = <&cpg 118>; 1338 }; 1339 1340 du: display@feb00000 { 1341 compatible = "renesas,du-r8a7793"; 1342 reg = <0 0xfeb00000 0 0x40000>; 1343 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1344 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1345 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; 1346 clock-names = "du.0", "du.1"; 1347 resets = <&cpg 724>; 1348 reset-names = "du.0"; 1349 status = "disabled"; 1350 1351 ports { 1352 #address-cells = <1>; 1353 #size-cells = <0>; 1354 1355 port@0 { 1356 reg = <0>; 1357 du_out_rgb: endpoint { 1358 }; 1359 }; 1360 port@1 { 1361 reg = <1>; 1362 du_out_lvds0: endpoint { 1363 remote-endpoint = <&lvds0_in>; 1364 }; 1365 }; 1366 }; 1367 }; 1368 1369 lvds0: lvds@feb90000 { 1370 compatible = "renesas,r8a7793-lvds"; 1371 reg = <0 0xfeb90000 0 0x1c>; 1372 clocks = <&cpg CPG_MOD 726>; 1373 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1374 resets = <&cpg 726>; 1375 1376 status = "disabled"; 1377 1378 ports { 1379 #address-cells = <1>; 1380 #size-cells = <0>; 1381 1382 port@0 { 1383 reg = <0>; 1384 lvds0_in: endpoint { 1385 remote-endpoint = <&du_out_lvds0>; 1386 }; 1387 }; 1388 port@1 { 1389 reg = <1>; 1390 lvds0_out: endpoint { 1391 }; 1392 }; 1393 }; 1394 }; 1395 1396 prr: chipid@ff000044 { 1397 compatible = "renesas,prr"; 1398 reg = <0 0xff000044 0 4>; 1399 }; 1400 1401 cmt0: timer@ffca0000 { 1402 compatible = "renesas,r8a7793-cmt0", 1403 "renesas,rcar-gen2-cmt0"; 1404 reg = <0 0xffca0000 0 0x1004>; 1405 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1407 clocks = <&cpg CPG_MOD 124>; 1408 clock-names = "fck"; 1409 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1410 resets = <&cpg 124>; 1411 1412 status = "disabled"; 1413 }; 1414 1415 cmt1: timer@e6130000 { 1416 compatible = "renesas,r8a7793-cmt1", 1417 "renesas,rcar-gen2-cmt1"; 1418 reg = <0 0xe6130000 0 0x1004>; 1419 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1420 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1427 clocks = <&cpg CPG_MOD 329>; 1428 clock-names = "fck"; 1429 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1430 resets = <&cpg 329>; 1431 1432 status = "disabled"; 1433 }; 1434 }; 1435 1436 thermal-zones { 1437 cpu_thermal: cpu-thermal { 1438 polling-delay-passive = <0>; 1439 polling-delay = <0>; 1440 1441 thermal-sensors = <&thermal>; 1442 1443 trips { 1444 cpu-crit { 1445 temperature = <95000>; 1446 hysteresis = <0>; 1447 type = "critical"; 1448 }; 1449 }; 1450 cooling-maps { 1451 }; 1452 }; 1453 }; 1454 1455 timer { 1456 compatible = "arm,armv7-timer"; 1457 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1458 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1459 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1460 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 1461 }; 1462 1463 /* External USB clock - can be overridden by the board */ 1464 usb_extal_clk: usb_extal { 1465 compatible = "fixed-clock"; 1466 #clock-cells = <0>; 1467 clock-frequency = <48000000>; 1468 }; 1469}; 1470