1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung's S3C2416 SoC device tree source
4 *
5 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
6 */
7
8#include <dt-bindings/clock/s3c2443.h>
9#include "s3c24xx.dtsi"
10#include "s3c2416-pinctrl.dtsi"
11
12/ {
13	model = "Samsung S3C2416 SoC";
14	compatible = "samsung,s3c2416";
15
16	aliases {
17		serial3 = &uart_3;
18	};
19
20	cpus {
21		#address-cells = <1>;
22		#size-cells = <0>;
23
24		cpu@0 {
25			device_type = "cpu";
26			compatible = "arm,arm926ej-s";
27			reg = <0x0>;
28		};
29	};
30
31	clocks: clock-controller@4c000000 {
32		compatible = "samsung,s3c2416-clock";
33		reg = <0x4c000000 0x40>;
34		#clock-cells = <1>;
35	};
36
37	uart_3: serial@5000c000 {
38		compatible = "samsung,s3c2440-uart";
39		reg = <0x5000C000 0x4000>;
40		interrupts = <1 18 24 4>, <1 18 25 4>;
41		clock-names = "uart", "clk_uart_baud2",
42				"clk_uart_baud3";
43		clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
44				<&clocks SCLK_UART>;
45		status = "disabled";
46	};
47
48	sdhci_1: sdhci@4ac00000 {
49		compatible = "samsung,s3c6410-sdhci";
50		reg = <0x4AC00000 0x100>;
51		interrupts = <0 0 21 3>;
52		clock-names = "hsmmc", "mmc_busclk.0",
53				"mmc_busclk.2";
54		clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
55				<&clocks MUX_HSMMC0>;
56		status = "disabled";
57	};
58
59	sdhci_0: sdhci@4a800000 {
60		compatible = "samsung,s3c6410-sdhci";
61		reg = <0x4A800000 0x100>;
62		interrupts = <0 0 20 3>;
63		clock-names = "hsmmc", "mmc_busclk.0",
64				"mmc_busclk.2";
65		clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
66				<&clocks MUX_HSMMC1>;
67		status = "disabled";
68	};
69};
70
71&i2c {
72	compatible = "samsung,s3c2440-i2c";
73	clocks = <&clocks PCLK_I2C0>;
74	clock-names = "i2c";
75};
76
77&intc {
78	compatible = "samsung,s3c2416-irq";
79};
80
81&pinctrl_0 {
82	compatible = "samsung,s3c2416-pinctrl";
83};
84
85&rtc {
86	compatible = "samsung,s3c2416-rtc";
87	clocks = <&clocks PCLK_RTC>;
88	clock-names = "rtc";
89};
90
91&timer {
92	clocks = <&clocks PCLK_PWM>;
93	clock-names = "timers";
94};
95
96&uart_0 {
97	compatible = "samsung,s3c2440-uart";
98	clock-names = "uart", "clk_uart_baud2",
99			"clk_uart_baud3";
100	clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
101			<&clocks SCLK_UART>;
102};
103
104&uart_1 {
105	compatible = "samsung,s3c2440-uart";
106	clock-names = "uart", "clk_uart_baud2",
107			"clk_uart_baud3";
108	clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
109			<&clocks SCLK_UART>;
110};
111
112&uart_2 {
113	compatible = "samsung,s3c2440-uart";
114	clock-names = "uart", "clk_uart_baud2",
115			"clk_uart_baud3";
116	clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
117			<&clocks SCLK_UART>;
118};
119
120&watchdog {
121	interrupts = <1 9 27 3>;
122	clocks = <&clocks PCLK_WDT>;
123	clock-names = "watchdog";
124};
125