1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2014 STMicroelectronics Limited.
4 * Author: Peter Griffin <peter.griffin@linaro.org>
5 */
6#include "stih418-clock.dtsi"
7#include "stih407-family.dtsi"
8#include "stih410-pinctrl.dtsi"
9/ {
10	cpus {
11		#address-cells = <1>;
12		#size-cells = <0>;
13		cpu@2 {
14			device_type = "cpu";
15			compatible = "arm,cortex-a9";
16			reg = <2>;
17			/* u-boot puts hpen in SBC dmem at 0xa4 offset */
18			cpu-release-addr = <0x94100A4>;
19		};
20		cpu@3 {
21			device_type = "cpu";
22			compatible = "arm,cortex-a9";
23			reg = <3>;
24			/* u-boot puts hpen in SBC dmem at 0xa4 offset */
25			cpu-release-addr = <0x94100A4>;
26		};
27	};
28
29	soc {
30		rng11: rng@8a8a000 {
31			status = "disabled";
32		};
33
34		usb2_picophy1: phy2@0 {
35			compatible = "st,stih407-usb2-phy";
36			reg = <0 0>;
37			#phy-cells = <0>;
38			st,syscfg = <&syscfg_core 0xf8 0xf4>;
39			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
40				 <&picophyreset STIH407_PICOPHY0_RESET>;
41			reset-names = "global", "port";
42		};
43
44		usb2_picophy2: phy3@0 {
45			compatible = "st,stih407-usb2-phy";
46			reg = <0 0>;
47			#phy-cells = <0>;
48			st,syscfg = <&syscfg_core 0xfc 0xf4>;
49			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
50				 <&picophyreset STIH407_PICOPHY1_RESET>;
51			reset-names = "global", "port";
52		};
53
54		ohci0: usb@9a03c00 {
55			compatible = "st,st-ohci-300x";
56			reg = <0x9a03c00 0x100>;
57			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
58			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
59			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
60				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
61			reset-names = "power", "softreset";
62			phys = <&usb2_picophy1>;
63			phy-names = "usb";
64		};
65
66		ehci0: usb@9a03e00 {
67			compatible = "st,st-ehci-300x";
68			reg = <0x9a03e00 0x100>;
69			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
70			pinctrl-names = "default";
71			pinctrl-0 = <&pinctrl_usb0>;
72			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
73			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
74				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
75			reset-names = "power", "softreset";
76			phys = <&usb2_picophy1>;
77			phy-names = "usb";
78		};
79
80		ohci1: usb@9a83c00 {
81			compatible = "st,st-ohci-300x";
82			reg = <0x9a83c00 0x100>;
83			interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
84			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
85			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
86				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
87			reset-names = "power", "softreset";
88			phys = <&usb2_picophy2>;
89			phy-names = "usb";
90		};
91
92		ehci1: usb@9a83e00 {
93			compatible = "st,st-ehci-300x";
94			reg = <0x9a83e00 0x100>;
95			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
96			pinctrl-names = "default";
97			pinctrl-0 = <&pinctrl_usb1>;
98			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
99			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
100				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
101			reset-names = "power", "softreset";
102			phys = <&usb2_picophy2>;
103			phy-names = "usb";
104		};
105
106		mmc0: sdhci@9060000 {
107			assigned-clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
108			assigned-clock-parents = <&clk_s_c0_pll1 0>;
109			assigned-clock-rates = <200000000>;
110		};
111
112		thermal@91a0000 {
113			compatible = "st,stih407-thermal";
114			reg = <0x91a0000 0x28>;
115			clock-names = "thermal";
116			clocks = <&clk_sysin>;
117			interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
118		};
119	};
120};
121