1/* 2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public 20 * License along with this file; if not, write to the Free 21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48#include "armv7-m.dtsi" 49#include <dt-bindings/clock/stm32fx-clock.h> 50#include <dt-bindings/mfd/stm32f4-rcc.h> 51 52/ { 53 #address-cells = <1>; 54 #size-cells = <1>; 55 56 clocks { 57 clk_hse: clk-hse { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <0>; 61 }; 62 63 clk_lse: clk-lse { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <32768>; 67 }; 68 69 clk_lsi: clk-lsi { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <32000>; 73 }; 74 75 clk_i2s_ckin: i2s-ckin { 76 #clock-cells = <0>; 77 compatible = "fixed-clock"; 78 clock-frequency = <0>; 79 }; 80 }; 81 82 soc { 83 romem: efuse@1fff7800 { 84 compatible = "st,stm32f4-otp"; 85 reg = <0x1fff7800 0x400>; 86 #address-cells = <1>; 87 #size-cells = <1>; 88 ts_cal1: calib@22c { 89 reg = <0x22c 0x2>; 90 }; 91 ts_cal2: calib@22e { 92 reg = <0x22e 0x2>; 93 }; 94 }; 95 96 timer2: timer@40000000 { 97 compatible = "st,stm32-timer"; 98 reg = <0x40000000 0x400>; 99 interrupts = <28>; 100 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>; 101 status = "disabled"; 102 }; 103 104 timers2: timers@40000000 { 105 #address-cells = <1>; 106 #size-cells = <0>; 107 compatible = "st,stm32-timers"; 108 reg = <0x40000000 0x400>; 109 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>; 110 clock-names = "int"; 111 status = "disabled"; 112 113 pwm { 114 compatible = "st,stm32-pwm"; 115 #pwm-cells = <3>; 116 status = "disabled"; 117 }; 118 119 timer@1 { 120 compatible = "st,stm32-timer-trigger"; 121 reg = <1>; 122 status = "disabled"; 123 }; 124 }; 125 126 timer3: timer@40000400 { 127 compatible = "st,stm32-timer"; 128 reg = <0x40000400 0x400>; 129 interrupts = <29>; 130 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; 131 status = "disabled"; 132 }; 133 134 timers3: timers@40000400 { 135 #address-cells = <1>; 136 #size-cells = <0>; 137 compatible = "st,stm32-timers"; 138 reg = <0x40000400 0x400>; 139 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; 140 clock-names = "int"; 141 status = "disabled"; 142 143 pwm { 144 compatible = "st,stm32-pwm"; 145 #pwm-cells = <3>; 146 status = "disabled"; 147 }; 148 149 timer@2 { 150 compatible = "st,stm32-timer-trigger"; 151 reg = <2>; 152 status = "disabled"; 153 }; 154 }; 155 156 timer4: timer@40000800 { 157 compatible = "st,stm32-timer"; 158 reg = <0x40000800 0x400>; 159 interrupts = <30>; 160 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; 161 status = "disabled"; 162 }; 163 164 timers4: timers@40000800 { 165 #address-cells = <1>; 166 #size-cells = <0>; 167 compatible = "st,stm32-timers"; 168 reg = <0x40000800 0x400>; 169 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; 170 clock-names = "int"; 171 status = "disabled"; 172 173 pwm { 174 compatible = "st,stm32-pwm"; 175 #pwm-cells = <3>; 176 status = "disabled"; 177 }; 178 179 timer@3 { 180 compatible = "st,stm32-timer-trigger"; 181 reg = <3>; 182 status = "disabled"; 183 }; 184 }; 185 186 timer5: timer@40000c00 { 187 compatible = "st,stm32-timer"; 188 reg = <0x40000c00 0x400>; 189 interrupts = <50>; 190 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>; 191 }; 192 193 timers5: timers@40000c00 { 194 #address-cells = <1>; 195 #size-cells = <0>; 196 compatible = "st,stm32-timers"; 197 reg = <0x40000C00 0x400>; 198 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>; 199 clock-names = "int"; 200 status = "disabled"; 201 202 pwm { 203 compatible = "st,stm32-pwm"; 204 #pwm-cells = <3>; 205 status = "disabled"; 206 }; 207 208 timer@4 { 209 compatible = "st,stm32-timer-trigger"; 210 reg = <4>; 211 status = "disabled"; 212 }; 213 }; 214 215 timer6: timer@40001000 { 216 compatible = "st,stm32-timer"; 217 reg = <0x40001000 0x400>; 218 interrupts = <54>; 219 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; 220 status = "disabled"; 221 }; 222 223 timers6: timers@40001000 { 224 #address-cells = <1>; 225 #size-cells = <0>; 226 compatible = "st,stm32-timers"; 227 reg = <0x40001000 0x400>; 228 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; 229 clock-names = "int"; 230 status = "disabled"; 231 232 timer@5 { 233 compatible = "st,stm32-timer-trigger"; 234 reg = <5>; 235 status = "disabled"; 236 }; 237 }; 238 239 timer7: timer@40001400 { 240 compatible = "st,stm32-timer"; 241 reg = <0x40001400 0x400>; 242 interrupts = <55>; 243 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; 244 status = "disabled"; 245 }; 246 247 timers7: timers@40001400 { 248 #address-cells = <1>; 249 #size-cells = <0>; 250 compatible = "st,stm32-timers"; 251 reg = <0x40001400 0x400>; 252 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; 253 clock-names = "int"; 254 status = "disabled"; 255 256 timer@6 { 257 compatible = "st,stm32-timer-trigger"; 258 reg = <6>; 259 status = "disabled"; 260 }; 261 }; 262 263 timers12: timers@40001800 { 264 #address-cells = <1>; 265 #size-cells = <0>; 266 compatible = "st,stm32-timers"; 267 reg = <0x40001800 0x400>; 268 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>; 269 clock-names = "int"; 270 status = "disabled"; 271 272 pwm { 273 compatible = "st,stm32-pwm"; 274 #pwm-cells = <3>; 275 status = "disabled"; 276 }; 277 278 timer@11 { 279 compatible = "st,stm32-timer-trigger"; 280 reg = <11>; 281 status = "disabled"; 282 }; 283 }; 284 285 timers13: timers@40001c00 { 286 compatible = "st,stm32-timers"; 287 reg = <0x40001C00 0x400>; 288 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>; 289 clock-names = "int"; 290 status = "disabled"; 291 292 pwm { 293 compatible = "st,stm32-pwm"; 294 #pwm-cells = <3>; 295 status = "disabled"; 296 }; 297 }; 298 299 timers14: timers@40002000 { 300 compatible = "st,stm32-timers"; 301 reg = <0x40002000 0x400>; 302 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>; 303 clock-names = "int"; 304 status = "disabled"; 305 306 pwm { 307 compatible = "st,stm32-pwm"; 308 #pwm-cells = <3>; 309 status = "disabled"; 310 }; 311 }; 312 313 rtc: rtc@40002800 { 314 compatible = "st,stm32-rtc"; 315 reg = <0x40002800 0x400>; 316 clocks = <&rcc 1 CLK_RTC>; 317 assigned-clocks = <&rcc 1 CLK_RTC>; 318 assigned-clock-parents = <&rcc 1 CLK_LSE>; 319 interrupt-parent = <&exti>; 320 interrupts = <17 1>; 321 st,syscfg = <&pwrcfg 0x00 0x100>; 322 status = "disabled"; 323 }; 324 325 iwdg: watchdog@40003000 { 326 compatible = "st,stm32-iwdg"; 327 reg = <0x40003000 0x400>; 328 clocks = <&clk_lsi>; 329 clock-names = "lsi"; 330 status = "disabled"; 331 }; 332 333 spi2: spi@40003800 { 334 #address-cells = <1>; 335 #size-cells = <0>; 336 compatible = "st,stm32f4-spi"; 337 reg = <0x40003800 0x400>; 338 interrupts = <36>; 339 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>; 340 status = "disabled"; 341 }; 342 343 spi3: spi@40003c00 { 344 #address-cells = <1>; 345 #size-cells = <0>; 346 compatible = "st,stm32f4-spi"; 347 reg = <0x40003c00 0x400>; 348 interrupts = <51>; 349 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>; 350 status = "disabled"; 351 }; 352 353 usart2: serial@40004400 { 354 compatible = "st,stm32-uart"; 355 reg = <0x40004400 0x400>; 356 interrupts = <38>; 357 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>; 358 status = "disabled"; 359 }; 360 361 usart3: serial@40004800 { 362 compatible = "st,stm32-uart"; 363 reg = <0x40004800 0x400>; 364 interrupts = <39>; 365 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>; 366 status = "disabled"; 367 dmas = <&dma1 1 4 0x400 0x0>, 368 <&dma1 3 4 0x400 0x0>; 369 dma-names = "rx", "tx"; 370 }; 371 372 usart4: serial@40004c00 { 373 compatible = "st,stm32-uart"; 374 reg = <0x40004c00 0x400>; 375 interrupts = <52>; 376 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>; 377 status = "disabled"; 378 }; 379 380 usart5: serial@40005000 { 381 compatible = "st,stm32-uart"; 382 reg = <0x40005000 0x400>; 383 interrupts = <53>; 384 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>; 385 status = "disabled"; 386 }; 387 388 i2c1: i2c@40005400 { 389 compatible = "st,stm32f4-i2c"; 390 reg = <0x40005400 0x400>; 391 interrupts = <31>, 392 <32>; 393 resets = <&rcc STM32F4_APB1_RESET(I2C1)>; 394 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>; 395 #address-cells = <1>; 396 #size-cells = <0>; 397 status = "disabled"; 398 }; 399 400 i2c3: i2c@40005c00 { 401 compatible = "st,stm32f4-i2c"; 402 reg = <0x40005c00 0x400>; 403 interrupts = <72>, 404 <73>; 405 resets = <&rcc STM32F4_APB1_RESET(I2C3)>; 406 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>; 407 #address-cells = <1>; 408 #size-cells = <0>; 409 status = "disabled"; 410 }; 411 412 dac: dac@40007400 { 413 compatible = "st,stm32f4-dac-core"; 414 reg = <0x40007400 0x400>; 415 resets = <&rcc STM32F4_APB1_RESET(DAC)>; 416 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>; 417 clock-names = "pclk"; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 status = "disabled"; 421 422 dac1: dac@1 { 423 compatible = "st,stm32-dac"; 424 #io-channel-cells = <1>; 425 reg = <1>; 426 status = "disabled"; 427 }; 428 429 dac2: dac@2 { 430 compatible = "st,stm32-dac"; 431 #io-channel-cells = <1>; 432 reg = <2>; 433 status = "disabled"; 434 }; 435 }; 436 437 usart7: serial@40007800 { 438 compatible = "st,stm32-uart"; 439 reg = <0x40007800 0x400>; 440 interrupts = <82>; 441 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>; 442 status = "disabled"; 443 }; 444 445 usart8: serial@40007c00 { 446 compatible = "st,stm32-uart"; 447 reg = <0x40007c00 0x400>; 448 interrupts = <83>; 449 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>; 450 status = "disabled"; 451 }; 452 453 timers1: timers@40010000 { 454 #address-cells = <1>; 455 #size-cells = <0>; 456 compatible = "st,stm32-timers"; 457 reg = <0x40010000 0x400>; 458 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>; 459 clock-names = "int"; 460 status = "disabled"; 461 462 pwm { 463 compatible = "st,stm32-pwm"; 464 #pwm-cells = <3>; 465 status = "disabled"; 466 }; 467 468 timer@0 { 469 compatible = "st,stm32-timer-trigger"; 470 reg = <0>; 471 status = "disabled"; 472 }; 473 }; 474 475 timers8: timers@40010400 { 476 #address-cells = <1>; 477 #size-cells = <0>; 478 compatible = "st,stm32-timers"; 479 reg = <0x40010400 0x400>; 480 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>; 481 clock-names = "int"; 482 status = "disabled"; 483 484 pwm { 485 compatible = "st,stm32-pwm"; 486 #pwm-cells = <3>; 487 status = "disabled"; 488 }; 489 490 timer@7 { 491 compatible = "st,stm32-timer-trigger"; 492 reg = <7>; 493 status = "disabled"; 494 }; 495 }; 496 497 usart1: serial@40011000 { 498 compatible = "st,stm32-uart"; 499 reg = <0x40011000 0x400>; 500 interrupts = <37>; 501 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>; 502 status = "disabled"; 503 dmas = <&dma2 2 4 0x400 0x0>, 504 <&dma2 7 4 0x400 0x0>; 505 dma-names = "rx", "tx"; 506 }; 507 508 usart6: serial@40011400 { 509 compatible = "st,stm32-uart"; 510 reg = <0x40011400 0x400>; 511 interrupts = <71>; 512 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>; 513 status = "disabled"; 514 }; 515 516 adc: adc@40012000 { 517 compatible = "st,stm32f4-adc-core"; 518 reg = <0x40012000 0x400>; 519 interrupts = <18>; 520 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>; 521 clock-names = "adc"; 522 interrupt-controller; 523 #interrupt-cells = <1>; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 status = "disabled"; 527 528 adc1: adc@0 { 529 compatible = "st,stm32f4-adc"; 530 #io-channel-cells = <1>; 531 reg = <0x0>; 532 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>; 533 interrupt-parent = <&adc>; 534 interrupts = <0>; 535 dmas = <&dma2 0 0 0x400 0x0>; 536 dma-names = "rx"; 537 status = "disabled"; 538 }; 539 540 adc2: adc@100 { 541 compatible = "st,stm32f4-adc"; 542 #io-channel-cells = <1>; 543 reg = <0x100>; 544 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>; 545 interrupt-parent = <&adc>; 546 interrupts = <1>; 547 dmas = <&dma2 3 1 0x400 0x0>; 548 dma-names = "rx"; 549 status = "disabled"; 550 }; 551 552 adc3: adc@200 { 553 compatible = "st,stm32f4-adc"; 554 #io-channel-cells = <1>; 555 reg = <0x200>; 556 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>; 557 interrupt-parent = <&adc>; 558 interrupts = <2>; 559 dmas = <&dma2 1 2 0x400 0x0>; 560 dma-names = "rx"; 561 status = "disabled"; 562 }; 563 }; 564 565 sdio: mmc@40012c00 { 566 compatible = "arm,pl180", "arm,primecell"; 567 arm,primecell-periphid = <0x00880180>; 568 reg = <0x40012c00 0x400>; 569 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>; 570 clock-names = "apb_pclk"; 571 interrupts = <49>; 572 max-frequency = <48000000>; 573 status = "disabled"; 574 }; 575 576 spi1: spi@40013000 { 577 #address-cells = <1>; 578 #size-cells = <0>; 579 compatible = "st,stm32f4-spi"; 580 reg = <0x40013000 0x400>; 581 interrupts = <35>; 582 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>; 583 status = "disabled"; 584 }; 585 586 spi4: spi@40013400 { 587 #address-cells = <1>; 588 #size-cells = <0>; 589 compatible = "st,stm32f4-spi"; 590 reg = <0x40013400 0x400>; 591 interrupts = <84>; 592 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>; 593 status = "disabled"; 594 }; 595 596 syscfg: syscon@40013800 { 597 compatible = "st,stm32-syscfg", "syscon"; 598 reg = <0x40013800 0x400>; 599 }; 600 601 exti: interrupt-controller@40013c00 { 602 compatible = "st,stm32-exti"; 603 interrupt-controller; 604 #interrupt-cells = <2>; 605 reg = <0x40013C00 0x400>; 606 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; 607 }; 608 609 timers9: timers@40014000 { 610 #address-cells = <1>; 611 #size-cells = <0>; 612 compatible = "st,stm32-timers"; 613 reg = <0x40014000 0x400>; 614 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>; 615 clock-names = "int"; 616 status = "disabled"; 617 618 pwm { 619 compatible = "st,stm32-pwm"; 620 #pwm-cells = <3>; 621 status = "disabled"; 622 }; 623 624 timer@8 { 625 compatible = "st,stm32-timer-trigger"; 626 reg = <8>; 627 status = "disabled"; 628 }; 629 }; 630 631 timers10: timers@40014400 { 632 compatible = "st,stm32-timers"; 633 reg = <0x40014400 0x400>; 634 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>; 635 clock-names = "int"; 636 status = "disabled"; 637 638 pwm { 639 compatible = "st,stm32-pwm"; 640 #pwm-cells = <3>; 641 status = "disabled"; 642 }; 643 }; 644 645 timers11: timers@40014800 { 646 compatible = "st,stm32-timers"; 647 reg = <0x40014800 0x400>; 648 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>; 649 clock-names = "int"; 650 status = "disabled"; 651 652 pwm { 653 compatible = "st,stm32-pwm"; 654 #pwm-cells = <3>; 655 status = "disabled"; 656 }; 657 }; 658 659 spi5: spi@40015000 { 660 #address-cells = <1>; 661 #size-cells = <0>; 662 compatible = "st,stm32f4-spi"; 663 reg = <0x40015000 0x400>; 664 interrupts = <85>; 665 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>; 666 dmas = <&dma2 3 2 0x400 0x0>, 667 <&dma2 4 2 0x400 0x0>; 668 dma-names = "rx", "tx"; 669 status = "disabled"; 670 }; 671 672 spi6: spi@40015400 { 673 #address-cells = <1>; 674 #size-cells = <0>; 675 compatible = "st,stm32f4-spi"; 676 reg = <0x40015400 0x400>; 677 interrupts = <86>; 678 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>; 679 status = "disabled"; 680 }; 681 682 pwrcfg: power-config@40007000 { 683 compatible = "st,stm32-power-config", "syscon"; 684 reg = <0x40007000 0x400>; 685 }; 686 687 ltdc: display-controller@40016800 { 688 compatible = "st,stm32-ltdc"; 689 reg = <0x40016800 0x200>; 690 interrupts = <88>, <89>; 691 resets = <&rcc STM32F4_APB2_RESET(LTDC)>; 692 clocks = <&rcc 1 CLK_LCD>; 693 clock-names = "lcd"; 694 status = "disabled"; 695 }; 696 697 crc: crc@40023000 { 698 compatible = "st,stm32f4-crc"; 699 reg = <0x40023000 0x400>; 700 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>; 701 status = "disabled"; 702 }; 703 704 rcc: rcc@40023800 { 705 #reset-cells = <1>; 706 #clock-cells = <2>; 707 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; 708 reg = <0x40023800 0x400>; 709 clocks = <&clk_hse>, <&clk_i2s_ckin>; 710 st,syscfg = <&pwrcfg>; 711 assigned-clocks = <&rcc 1 CLK_HSE_RTC>; 712 assigned-clock-rates = <1000000>; 713 }; 714 715 dma1: dma-controller@40026000 { 716 compatible = "st,stm32-dma"; 717 reg = <0x40026000 0x400>; 718 interrupts = <11>, 719 <12>, 720 <13>, 721 <14>, 722 <15>, 723 <16>, 724 <17>, 725 <47>; 726 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>; 727 #dma-cells = <4>; 728 }; 729 730 dma2: dma-controller@40026400 { 731 compatible = "st,stm32-dma"; 732 reg = <0x40026400 0x400>; 733 interrupts = <56>, 734 <57>, 735 <58>, 736 <59>, 737 <60>, 738 <68>, 739 <69>, 740 <70>; 741 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>; 742 #dma-cells = <4>; 743 st,mem2mem; 744 }; 745 746 mac: ethernet@40028000 { 747 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a"; 748 reg = <0x40028000 0x8000>; 749 reg-names = "stmmaceth"; 750 interrupts = <61>; 751 interrupt-names = "macirq"; 752 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; 753 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>, 754 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>, 755 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>; 756 st,syscon = <&syscfg 0x4>; 757 snps,pbl = <8>; 758 snps,mixed-burst; 759 status = "disabled"; 760 }; 761 762 usbotg_hs: usb@40040000 { 763 compatible = "snps,dwc2"; 764 reg = <0x40040000 0x40000>; 765 interrupts = <77>; 766 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>; 767 clock-names = "otg"; 768 status = "disabled"; 769 }; 770 771 usbotg_fs: usb@50000000 { 772 compatible = "st,stm32f4x9-fsotg"; 773 reg = <0x50000000 0x40000>; 774 interrupts = <67>; 775 clocks = <&rcc 0 39>; 776 clock-names = "otg"; 777 status = "disabled"; 778 }; 779 780 dcmi: dcmi@50050000 { 781 compatible = "st,stm32-dcmi"; 782 reg = <0x50050000 0x400>; 783 interrupts = <78>; 784 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>; 785 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>; 786 clock-names = "mclk"; 787 pinctrl-names = "default"; 788 pinctrl-0 = <&dcmi_pins>; 789 dmas = <&dma2 1 1 0x414 0x3>; 790 dma-names = "tx"; 791 status = "disabled"; 792 }; 793 794 rng: rng@50060800 { 795 compatible = "st,stm32-rng"; 796 reg = <0x50060800 0x400>; 797 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>; 798 799 }; 800 }; 801}; 802 803&systick { 804 clocks = <&rcc 1 SYSTICK>; 805 status = "okay"; 806}; 807