1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7
8/ {
9	#address-cells = <1>;
10	#size-cells = <1>;
11
12	cpus {
13		#address-cells = <1>;
14		#size-cells = <0>;
15
16		cpu0: cpu@0 {
17			compatible = "arm,cortex-a7";
18			device_type = "cpu";
19			reg = <0>;
20		};
21	};
22
23	arm-pmu {
24		compatible = "arm,cortex-a7-pmu";
25		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
26		interrupt-affinity = <&cpu0>;
27		interrupt-parent = <&intc>;
28	};
29
30	clocks {
31		clk_axi: clk-axi {
32			#clock-cells = <0>;
33			compatible = "fixed-clock";
34			clock-frequency = <266500000>;
35		};
36
37		clk_hse: clk-hse {
38			#clock-cells = <0>;
39			compatible = "fixed-clock";
40			clock-frequency = <24000000>;
41		};
42
43		clk_hsi: clk-hsi {
44			#clock-cells = <0>;
45			compatible = "fixed-clock";
46			clock-frequency = <64000000>;
47		};
48
49		clk_lsi: clk-lsi {
50			#clock-cells = <0>;
51			compatible = "fixed-clock";
52			clock-frequency = <32000>;
53		};
54
55		clk_pclk3: clk-pclk3 {
56			#clock-cells = <0>;
57			compatible = "fixed-clock";
58			clock-frequency = <104438965>;
59		};
60
61		clk_pclk4: clk-pclk4 {
62			#clock-cells = <0>;
63			compatible = "fixed-clock";
64			clock-frequency = <133250000>;
65		};
66
67		clk_pll4_p: clk-pll4_p {
68			#clock-cells = <0>;
69			compatible = "fixed-clock";
70			clock-frequency = <50000000>;
71		};
72
73		clk_pll4_r: clk-pll4_r {
74			#clock-cells = <0>;
75			compatible = "fixed-clock";
76			clock-frequency = <99000000>;
77		};
78	};
79
80	intc: interrupt-controller@a0021000 {
81		compatible = "arm,cortex-a7-gic";
82		#interrupt-cells = <3>;
83		interrupt-controller;
84		reg = <0xa0021000 0x1000>,
85		      <0xa0022000 0x2000>;
86	};
87
88	psci {
89		compatible = "arm,psci-1.0";
90		method = "smc";
91	};
92
93	timer {
94		compatible = "arm,armv7-timer";
95		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
96			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
97			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
98			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
99		interrupt-parent = <&intc>;
100		always-on;
101	};
102
103	soc {
104		compatible = "simple-bus";
105		#address-cells = <1>;
106		#size-cells = <1>;
107		interrupt-parent = <&intc>;
108		ranges;
109
110		uart4: serial@40010000 {
111			compatible = "st,stm32h7-uart";
112			reg = <0x40010000 0x400>;
113			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
114			clocks = <&clk_hsi>;
115			status = "disabled";
116		};
117
118		syscfg: syscon@50020000 {
119			compatible = "st,stm32mp157-syscfg", "syscon";
120			reg = <0x50020000 0x400>;
121			clocks = <&clk_pclk3>;
122		};
123
124		sdmmc1: mmc@58005000 {
125			compatible = "arm,pl18x", "arm,primecell";
126			arm,primecell-periphid = <0x00253180>;
127			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
128			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
129			interrupt-names = "cmd_irq";
130			clocks = <&clk_pll4_p>;
131			clock-names = "apb_pclk";
132			cap-sd-highspeed;
133			cap-mmc-highspeed;
134			max-frequency = <120000000>;
135			status = "disabled";
136		};
137
138		iwdg2: watchdog@5a002000 {
139			compatible = "st,stm32mp1-iwdg";
140			reg = <0x5a002000 0x400>;
141			clocks = <&clk_pclk4>, <&clk_lsi>;
142			clock-names = "pclk", "lsi";
143			status = "disabled";
144		};
145
146		bsec: efuse@5c005000 {
147			compatible = "st,stm32mp15-bsec";
148			reg = <0x5c005000 0x400>;
149			#address-cells = <1>;
150			#size-cells = <1>;
151
152			part_number_otp: part_number_otp@4 {
153				reg = <0x4 0x2>;
154			};
155			ts_cal1: calib@5c {
156				reg = <0x5c 0x2>;
157			};
158			ts_cal2: calib@5e {
159				reg = <0x5e 0x2>;
160			};
161		};
162
163		/*
164		 * Break node order to solve dependency probe issue between
165		 * pinctrl and exti.
166		 */
167		pinctrl: pin-controller@50002000 {
168			#address-cells = <1>;
169			#size-cells = <1>;
170			compatible = "st,stm32mp135-pinctrl";
171			ranges = <0 0x50002000 0x8400>;
172			pins-are-numbered;
173
174			gpioa: gpio@50002000 {
175				gpio-controller;
176				#gpio-cells = <2>;
177				interrupt-controller;
178				#interrupt-cells = <2>;
179				reg = <0x0 0x400>;
180				clocks = <&clk_pclk4>;
181				st,bank-name = "GPIOA";
182				ngpios = <16>;
183				gpio-ranges = <&pinctrl 0 0 16>;
184			};
185
186			gpiob: gpio@50003000 {
187				gpio-controller;
188				#gpio-cells = <2>;
189				interrupt-controller;
190				#interrupt-cells = <2>;
191				reg = <0x1000 0x400>;
192				clocks = <&clk_pclk4>;
193				st,bank-name = "GPIOB";
194				ngpios = <16>;
195				gpio-ranges = <&pinctrl 0 16 16>;
196			};
197
198			gpioc: gpio@50004000 {
199				gpio-controller;
200				#gpio-cells = <2>;
201				interrupt-controller;
202				#interrupt-cells = <2>;
203				reg = <0x2000 0x400>;
204				clocks = <&clk_pclk4>;
205				st,bank-name = "GPIOC";
206				ngpios = <16>;
207				gpio-ranges = <&pinctrl 0 32 16>;
208			};
209
210			gpiod: gpio@50005000 {
211				gpio-controller;
212				#gpio-cells = <2>;
213				interrupt-controller;
214				#interrupt-cells = <2>;
215				reg = <0x3000 0x400>;
216				clocks = <&clk_pclk4>;
217				st,bank-name = "GPIOD";
218				ngpios = <16>;
219				gpio-ranges = <&pinctrl 0 48 16>;
220			};
221
222			gpioe: gpio@50006000 {
223				gpio-controller;
224				#gpio-cells = <2>;
225				interrupt-controller;
226				#interrupt-cells = <2>;
227				reg = <0x4000 0x400>;
228				clocks = <&clk_pclk4>;
229				st,bank-name = "GPIOE";
230				ngpios = <16>;
231				gpio-ranges = <&pinctrl 0 64 16>;
232			};
233
234			gpiof: gpio@50007000 {
235				gpio-controller;
236				#gpio-cells = <2>;
237				interrupt-controller;
238				#interrupt-cells = <2>;
239				reg = <0x5000 0x400>;
240				clocks = <&clk_pclk4>;
241				st,bank-name = "GPIOF";
242				ngpios = <16>;
243				gpio-ranges = <&pinctrl 0 80 16>;
244			};
245
246			gpiog: gpio@50008000 {
247				gpio-controller;
248				#gpio-cells = <2>;
249				interrupt-controller;
250				#interrupt-cells = <2>;
251				reg = <0x6000 0x400>;
252				clocks = <&clk_pclk4>;
253				st,bank-name = "GPIOG";
254				ngpios = <16>;
255				gpio-ranges = <&pinctrl 0 96 16>;
256			};
257
258			gpioh: gpio@50009000 {
259				gpio-controller;
260				#gpio-cells = <2>;
261				interrupt-controller;
262				#interrupt-cells = <2>;
263				reg = <0x7000 0x400>;
264				clocks = <&clk_pclk4>;
265				st,bank-name = "GPIOH";
266				ngpios = <15>;
267				gpio-ranges = <&pinctrl 0 112 15>;
268			};
269
270			gpioi: gpio@5000a000 {
271				gpio-controller;
272				#gpio-cells = <2>;
273				interrupt-controller;
274				#interrupt-cells = <2>;
275				reg = <0x8000 0x400>;
276				clocks = <&clk_pclk4>;
277				st,bank-name = "GPIOI";
278				ngpios = <8>;
279				gpio-ranges = <&pinctrl 0 128 8>;
280			};
281		};
282	};
283};
284