1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/stm32mp1-clks.h>
8#include <dt-bindings/reset/stm32mp1-resets.h>
9
10/ {
11	#address-cells = <1>;
12	#size-cells = <1>;
13
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu0: cpu@0 {
19			compatible = "arm,cortex-a7";
20			clock-frequency = <650000000>;
21			device_type = "cpu";
22			reg = <0>;
23		};
24	};
25
26	arm-pmu {
27		compatible = "arm,cortex-a7-pmu";
28		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
29		interrupt-affinity = <&cpu0>;
30		interrupt-parent = <&intc>;
31	};
32
33	psci {
34		compatible = "arm,psci-1.0";
35		method = "smc";
36	};
37
38	firmware {
39		optee: optee {
40			compatible = "linaro,optee-tz";
41			method = "smc";
42			status = "disabled";
43		};
44	};
45
46	intc: interrupt-controller@a0021000 {
47		compatible = "arm,cortex-a7-gic";
48		#interrupt-cells = <3>;
49		interrupt-controller;
50		reg = <0xa0021000 0x1000>,
51		      <0xa0022000 0x2000>;
52	};
53
54	timer {
55		compatible = "arm,armv7-timer";
56		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
57			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
58			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
59			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
60		interrupt-parent = <&intc>;
61	};
62
63	clocks {
64		clk_hse: clk-hse {
65			#clock-cells = <0>;
66			compatible = "fixed-clock";
67			clock-frequency = <24000000>;
68		};
69
70		clk_hsi: clk-hsi {
71			#clock-cells = <0>;
72			compatible = "fixed-clock";
73			clock-frequency = <64000000>;
74		};
75
76		clk_lse: clk-lse {
77			#clock-cells = <0>;
78			compatible = "fixed-clock";
79			clock-frequency = <32768>;
80		};
81
82		clk_lsi: clk-lsi {
83			#clock-cells = <0>;
84			compatible = "fixed-clock";
85			clock-frequency = <32000>;
86		};
87
88		clk_csi: clk-csi {
89			#clock-cells = <0>;
90			compatible = "fixed-clock";
91			clock-frequency = <4000000>;
92		};
93	};
94
95	thermal-zones {
96		cpu_thermal: cpu-thermal {
97			polling-delay-passive = <0>;
98			polling-delay = <0>;
99			thermal-sensors = <&dts>;
100
101			trips {
102				cpu_alert1: cpu-alert1 {
103					temperature = <85000>;
104					hysteresis = <0>;
105					type = "passive";
106				};
107
108				cpu-crit {
109					temperature = <120000>;
110					hysteresis = <0>;
111					type = "critical";
112				};
113			};
114
115			cooling-maps {
116			};
117		};
118	};
119
120	booster: regulator-booster {
121		compatible = "st,stm32mp1-booster";
122		st,syscfg = <&syscfg>;
123		status = "disabled";
124	};
125
126	soc {
127		compatible = "simple-bus";
128		#address-cells = <1>;
129		#size-cells = <1>;
130		interrupt-parent = <&intc>;
131		ranges;
132
133		timers2: timer@40000000 {
134			#address-cells = <1>;
135			#size-cells = <0>;
136			compatible = "st,stm32-timers";
137			reg = <0x40000000 0x400>;
138			clocks = <&rcc TIM2_K>;
139			clock-names = "int";
140			dmas = <&dmamux1 18 0x400 0x1>,
141			       <&dmamux1 19 0x400 0x1>,
142			       <&dmamux1 20 0x400 0x1>,
143			       <&dmamux1 21 0x400 0x1>,
144			       <&dmamux1 22 0x400 0x1>;
145			dma-names = "ch1", "ch2", "ch3", "ch4", "up";
146			status = "disabled";
147
148			pwm {
149				compatible = "st,stm32-pwm";
150				#pwm-cells = <3>;
151				status = "disabled";
152			};
153
154			timer@1 {
155				compatible = "st,stm32h7-timer-trigger";
156				reg = <1>;
157				status = "disabled";
158			};
159
160			counter {
161				compatible = "st,stm32-timer-counter";
162				status = "disabled";
163			};
164		};
165
166		timers3: timer@40001000 {
167			#address-cells = <1>;
168			#size-cells = <0>;
169			compatible = "st,stm32-timers";
170			reg = <0x40001000 0x400>;
171			clocks = <&rcc TIM3_K>;
172			clock-names = "int";
173			dmas = <&dmamux1 23 0x400 0x1>,
174			       <&dmamux1 24 0x400 0x1>,
175			       <&dmamux1 25 0x400 0x1>,
176			       <&dmamux1 26 0x400 0x1>,
177			       <&dmamux1 27 0x400 0x1>,
178			       <&dmamux1 28 0x400 0x1>;
179			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
180			status = "disabled";
181
182			pwm {
183				compatible = "st,stm32-pwm";
184				#pwm-cells = <3>;
185				status = "disabled";
186			};
187
188			timer@2 {
189				compatible = "st,stm32h7-timer-trigger";
190				reg = <2>;
191				status = "disabled";
192			};
193
194			counter {
195				compatible = "st,stm32-timer-counter";
196				status = "disabled";
197			};
198		};
199
200		timers4: timer@40002000 {
201			#address-cells = <1>;
202			#size-cells = <0>;
203			compatible = "st,stm32-timers";
204			reg = <0x40002000 0x400>;
205			clocks = <&rcc TIM4_K>;
206			clock-names = "int";
207			dmas = <&dmamux1 29 0x400 0x1>,
208			       <&dmamux1 30 0x400 0x1>,
209			       <&dmamux1 31 0x400 0x1>,
210			       <&dmamux1 32 0x400 0x1>;
211			dma-names = "ch1", "ch2", "ch3", "ch4";
212			status = "disabled";
213
214			pwm {
215				compatible = "st,stm32-pwm";
216				#pwm-cells = <3>;
217				status = "disabled";
218			};
219
220			timer@3 {
221				compatible = "st,stm32h7-timer-trigger";
222				reg = <3>;
223				status = "disabled";
224			};
225
226			counter {
227				compatible = "st,stm32-timer-counter";
228				status = "disabled";
229			};
230		};
231
232		timers5: timer@40003000 {
233			#address-cells = <1>;
234			#size-cells = <0>;
235			compatible = "st,stm32-timers";
236			reg = <0x40003000 0x400>;
237			clocks = <&rcc TIM5_K>;
238			clock-names = "int";
239			dmas = <&dmamux1 55 0x400 0x1>,
240			       <&dmamux1 56 0x400 0x1>,
241			       <&dmamux1 57 0x400 0x1>,
242			       <&dmamux1 58 0x400 0x1>,
243			       <&dmamux1 59 0x400 0x1>,
244			       <&dmamux1 60 0x400 0x1>;
245			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
246			status = "disabled";
247
248			pwm {
249				compatible = "st,stm32-pwm";
250				#pwm-cells = <3>;
251				status = "disabled";
252			};
253
254			timer@4 {
255				compatible = "st,stm32h7-timer-trigger";
256				reg = <4>;
257				status = "disabled";
258			};
259
260			counter {
261				compatible = "st,stm32-timer-counter";
262				status = "disabled";
263			};
264		};
265
266		timers6: timer@40004000 {
267			#address-cells = <1>;
268			#size-cells = <0>;
269			compatible = "st,stm32-timers";
270			reg = <0x40004000 0x400>;
271			clocks = <&rcc TIM6_K>;
272			clock-names = "int";
273			dmas = <&dmamux1 69 0x400 0x1>;
274			dma-names = "up";
275			status = "disabled";
276
277			timer@5 {
278				compatible = "st,stm32h7-timer-trigger";
279				reg = <5>;
280				status = "disabled";
281			};
282		};
283
284		timers7: timer@40005000 {
285			#address-cells = <1>;
286			#size-cells = <0>;
287			compatible = "st,stm32-timers";
288			reg = <0x40005000 0x400>;
289			clocks = <&rcc TIM7_K>;
290			clock-names = "int";
291			dmas = <&dmamux1 70 0x400 0x1>;
292			dma-names = "up";
293			status = "disabled";
294
295			timer@6 {
296				compatible = "st,stm32h7-timer-trigger";
297				reg = <6>;
298				status = "disabled";
299			};
300		};
301
302		timers12: timer@40006000 {
303			#address-cells = <1>;
304			#size-cells = <0>;
305			compatible = "st,stm32-timers";
306			reg = <0x40006000 0x400>;
307			clocks = <&rcc TIM12_K>;
308			clock-names = "int";
309			status = "disabled";
310
311			pwm {
312				compatible = "st,stm32-pwm";
313				#pwm-cells = <3>;
314				status = "disabled";
315			};
316
317			timer@11 {
318				compatible = "st,stm32h7-timer-trigger";
319				reg = <11>;
320				status = "disabled";
321			};
322		};
323
324		timers13: timer@40007000 {
325			#address-cells = <1>;
326			#size-cells = <0>;
327			compatible = "st,stm32-timers";
328			reg = <0x40007000 0x400>;
329			clocks = <&rcc TIM13_K>;
330			clock-names = "int";
331			status = "disabled";
332
333			pwm {
334				compatible = "st,stm32-pwm";
335				#pwm-cells = <3>;
336				status = "disabled";
337			};
338
339			timer@12 {
340				compatible = "st,stm32h7-timer-trigger";
341				reg = <12>;
342				status = "disabled";
343			};
344		};
345
346		timers14: timer@40008000 {
347			#address-cells = <1>;
348			#size-cells = <0>;
349			compatible = "st,stm32-timers";
350			reg = <0x40008000 0x400>;
351			clocks = <&rcc TIM14_K>;
352			clock-names = "int";
353			status = "disabled";
354
355			pwm {
356				compatible = "st,stm32-pwm";
357				#pwm-cells = <3>;
358				status = "disabled";
359			};
360
361			timer@13 {
362				compatible = "st,stm32h7-timer-trigger";
363				reg = <13>;
364				status = "disabled";
365			};
366		};
367
368		lptimer1: timer@40009000 {
369			#address-cells = <1>;
370			#size-cells = <0>;
371			compatible = "st,stm32-lptimer";
372			reg = <0x40009000 0x400>;
373			interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
374			clocks = <&rcc LPTIM1_K>;
375			clock-names = "mux";
376			wakeup-source;
377			status = "disabled";
378
379			pwm {
380				compatible = "st,stm32-pwm-lp";
381				#pwm-cells = <3>;
382				status = "disabled";
383			};
384
385			trigger@0 {
386				compatible = "st,stm32-lptimer-trigger";
387				reg = <0>;
388				status = "disabled";
389			};
390
391			counter {
392				compatible = "st,stm32-lptimer-counter";
393				status = "disabled";
394			};
395		};
396
397		spi2: spi@4000b000 {
398			#address-cells = <1>;
399			#size-cells = <0>;
400			compatible = "st,stm32h7-spi";
401			reg = <0x4000b000 0x400>;
402			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
403			clocks = <&rcc SPI2_K>;
404			resets = <&rcc SPI2_R>;
405			dmas = <&dmamux1 39 0x400 0x05>,
406			       <&dmamux1 40 0x400 0x05>;
407			dma-names = "rx", "tx";
408			status = "disabled";
409		};
410
411		i2s2: audio-controller@4000b000 {
412			compatible = "st,stm32h7-i2s";
413			#sound-dai-cells = <0>;
414			reg = <0x4000b000 0x400>;
415			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
416			dmas = <&dmamux1 39 0x400 0x01>,
417			       <&dmamux1 40 0x400 0x01>;
418			dma-names = "rx", "tx";
419			status = "disabled";
420		};
421
422		spi3: spi@4000c000 {
423			#address-cells = <1>;
424			#size-cells = <0>;
425			compatible = "st,stm32h7-spi";
426			reg = <0x4000c000 0x400>;
427			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
428			clocks = <&rcc SPI3_K>;
429			resets = <&rcc SPI3_R>;
430			dmas = <&dmamux1 61 0x400 0x05>,
431			       <&dmamux1 62 0x400 0x05>;
432			dma-names = "rx", "tx";
433			status = "disabled";
434		};
435
436		i2s3: audio-controller@4000c000 {
437			compatible = "st,stm32h7-i2s";
438			#sound-dai-cells = <0>;
439			reg = <0x4000c000 0x400>;
440			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
441			dmas = <&dmamux1 61 0x400 0x01>,
442			       <&dmamux1 62 0x400 0x01>;
443			dma-names = "rx", "tx";
444			status = "disabled";
445		};
446
447		spdifrx: audio-controller@4000d000 {
448			compatible = "st,stm32h7-spdifrx";
449			#sound-dai-cells = <0>;
450			reg = <0x4000d000 0x400>;
451			clocks = <&rcc SPDIF_K>;
452			clock-names = "kclk";
453			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
454			dmas = <&dmamux1 93 0x400 0x01>,
455			       <&dmamux1 94 0x400 0x01>;
456			dma-names = "rx", "rx-ctrl";
457			status = "disabled";
458		};
459
460		usart2: serial@4000e000 {
461			compatible = "st,stm32h7-uart";
462			reg = <0x4000e000 0x400>;
463			interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
464			clocks = <&rcc USART2_K>;
465			wakeup-source;
466			status = "disabled";
467		};
468
469		usart3: serial@4000f000 {
470			compatible = "st,stm32h7-uart";
471			reg = <0x4000f000 0x400>;
472			interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
473			clocks = <&rcc USART3_K>;
474			wakeup-source;
475			status = "disabled";
476		};
477
478		uart4: serial@40010000 {
479			compatible = "st,stm32h7-uart";
480			reg = <0x40010000 0x400>;
481			interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
482			clocks = <&rcc UART4_K>;
483			wakeup-source;
484			status = "disabled";
485		};
486
487		uart5: serial@40011000 {
488			compatible = "st,stm32h7-uart";
489			reg = <0x40011000 0x400>;
490			interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
491			clocks = <&rcc UART5_K>;
492			wakeup-source;
493			status = "disabled";
494		};
495
496		i2c1: i2c@40012000 {
497			compatible = "st,stm32mp15-i2c";
498			reg = <0x40012000 0x400>;
499			interrupt-names = "event", "error";
500			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
501				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
502			clocks = <&rcc I2C1_K>;
503			resets = <&rcc I2C1_R>;
504			#address-cells = <1>;
505			#size-cells = <0>;
506			st,syscfg-fmp = <&syscfg 0x4 0x1>;
507			wakeup-source;
508			i2c-analog-filter;
509			status = "disabled";
510		};
511
512		i2c2: i2c@40013000 {
513			compatible = "st,stm32mp15-i2c";
514			reg = <0x40013000 0x400>;
515			interrupt-names = "event", "error";
516			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
517				     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
518			clocks = <&rcc I2C2_K>;
519			resets = <&rcc I2C2_R>;
520			#address-cells = <1>;
521			#size-cells = <0>;
522			st,syscfg-fmp = <&syscfg 0x4 0x2>;
523			wakeup-source;
524			i2c-analog-filter;
525			status = "disabled";
526		};
527
528		i2c3: i2c@40014000 {
529			compatible = "st,stm32mp15-i2c";
530			reg = <0x40014000 0x400>;
531			interrupt-names = "event", "error";
532			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
533				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
534			clocks = <&rcc I2C3_K>;
535			resets = <&rcc I2C3_R>;
536			#address-cells = <1>;
537			#size-cells = <0>;
538			st,syscfg-fmp = <&syscfg 0x4 0x4>;
539			wakeup-source;
540			i2c-analog-filter;
541			status = "disabled";
542		};
543
544		i2c5: i2c@40015000 {
545			compatible = "st,stm32mp15-i2c";
546			reg = <0x40015000 0x400>;
547			interrupt-names = "event", "error";
548			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
549				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
550			clocks = <&rcc I2C5_K>;
551			resets = <&rcc I2C5_R>;
552			#address-cells = <1>;
553			#size-cells = <0>;
554			st,syscfg-fmp = <&syscfg 0x4 0x10>;
555			wakeup-source;
556			i2c-analog-filter;
557			status = "disabled";
558		};
559
560		cec: cec@40016000 {
561			compatible = "st,stm32-cec";
562			reg = <0x40016000 0x400>;
563			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
564			clocks = <&rcc CEC_K>, <&clk_lse>;
565			clock-names = "cec", "hdmi-cec";
566			status = "disabled";
567		};
568
569		dac: dac@40017000 {
570			compatible = "st,stm32h7-dac-core";
571			reg = <0x40017000 0x400>;
572			clocks = <&rcc DAC12>;
573			clock-names = "pclk";
574			#address-cells = <1>;
575			#size-cells = <0>;
576			status = "disabled";
577
578			dac1: dac@1 {
579				compatible = "st,stm32-dac";
580				#io-channel-cells = <1>;
581				reg = <1>;
582				status = "disabled";
583			};
584
585			dac2: dac@2 {
586				compatible = "st,stm32-dac";
587				#io-channel-cells = <1>;
588				reg = <2>;
589				status = "disabled";
590			};
591		};
592
593		uart7: serial@40018000 {
594			compatible = "st,stm32h7-uart";
595			reg = <0x40018000 0x400>;
596			interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
597			clocks = <&rcc UART7_K>;
598			wakeup-source;
599			status = "disabled";
600		};
601
602		uart8: serial@40019000 {
603			compatible = "st,stm32h7-uart";
604			reg = <0x40019000 0x400>;
605			interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
606			clocks = <&rcc UART8_K>;
607			wakeup-source;
608			status = "disabled";
609		};
610
611		timers1: timer@44000000 {
612			#address-cells = <1>;
613			#size-cells = <0>;
614			compatible = "st,stm32-timers";
615			reg = <0x44000000 0x400>;
616			clocks = <&rcc TIM1_K>;
617			clock-names = "int";
618			dmas = <&dmamux1 11 0x400 0x1>,
619			       <&dmamux1 12 0x400 0x1>,
620			       <&dmamux1 13 0x400 0x1>,
621			       <&dmamux1 14 0x400 0x1>,
622			       <&dmamux1 15 0x400 0x1>,
623			       <&dmamux1 16 0x400 0x1>,
624			       <&dmamux1 17 0x400 0x1>;
625			dma-names = "ch1", "ch2", "ch3", "ch4",
626				    "up", "trig", "com";
627			status = "disabled";
628
629			pwm {
630				compatible = "st,stm32-pwm";
631				#pwm-cells = <3>;
632				status = "disabled";
633			};
634
635			timer@0 {
636				compatible = "st,stm32h7-timer-trigger";
637				reg = <0>;
638				status = "disabled";
639			};
640
641			counter {
642				compatible = "st,stm32-timer-counter";
643				status = "disabled";
644			};
645		};
646
647		timers8: timer@44001000 {
648			#address-cells = <1>;
649			#size-cells = <0>;
650			compatible = "st,stm32-timers";
651			reg = <0x44001000 0x400>;
652			clocks = <&rcc TIM8_K>;
653			clock-names = "int";
654			dmas = <&dmamux1 47 0x400 0x1>,
655			       <&dmamux1 48 0x400 0x1>,
656			       <&dmamux1 49 0x400 0x1>,
657			       <&dmamux1 50 0x400 0x1>,
658			       <&dmamux1 51 0x400 0x1>,
659			       <&dmamux1 52 0x400 0x1>,
660			       <&dmamux1 53 0x400 0x1>;
661			dma-names = "ch1", "ch2", "ch3", "ch4",
662				    "up", "trig", "com";
663			status = "disabled";
664
665			pwm {
666				compatible = "st,stm32-pwm";
667				#pwm-cells = <3>;
668				status = "disabled";
669			};
670
671			timer@7 {
672				compatible = "st,stm32h7-timer-trigger";
673				reg = <7>;
674				status = "disabled";
675			};
676
677			counter {
678				compatible = "st,stm32-timer-counter";
679				status = "disabled";
680			};
681		};
682
683		usart6: serial@44003000 {
684			compatible = "st,stm32h7-uart";
685			reg = <0x44003000 0x400>;
686			interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
687			clocks = <&rcc USART6_K>;
688			wakeup-source;
689			status = "disabled";
690		};
691
692		spi1: spi@44004000 {
693			#address-cells = <1>;
694			#size-cells = <0>;
695			compatible = "st,stm32h7-spi";
696			reg = <0x44004000 0x400>;
697			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
698			clocks = <&rcc SPI1_K>;
699			resets = <&rcc SPI1_R>;
700			dmas = <&dmamux1 37 0x400 0x05>,
701			       <&dmamux1 38 0x400 0x05>;
702			dma-names = "rx", "tx";
703			status = "disabled";
704		};
705
706		i2s1: audio-controller@44004000 {
707			compatible = "st,stm32h7-i2s";
708			#sound-dai-cells = <0>;
709			reg = <0x44004000 0x400>;
710			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
711			dmas = <&dmamux1 37 0x400 0x01>,
712			       <&dmamux1 38 0x400 0x01>;
713			dma-names = "rx", "tx";
714			status = "disabled";
715		};
716
717		spi4: spi@44005000 {
718			#address-cells = <1>;
719			#size-cells = <0>;
720			compatible = "st,stm32h7-spi";
721			reg = <0x44005000 0x400>;
722			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
723			clocks = <&rcc SPI4_K>;
724			resets = <&rcc SPI4_R>;
725			dmas = <&dmamux1 83 0x400 0x05>,
726			       <&dmamux1 84 0x400 0x05>;
727			dma-names = "rx", "tx";
728			status = "disabled";
729		};
730
731		timers15: timer@44006000 {
732			#address-cells = <1>;
733			#size-cells = <0>;
734			compatible = "st,stm32-timers";
735			reg = <0x44006000 0x400>;
736			clocks = <&rcc TIM15_K>;
737			clock-names = "int";
738			dmas = <&dmamux1 105 0x400 0x1>,
739			       <&dmamux1 106 0x400 0x1>,
740			       <&dmamux1 107 0x400 0x1>,
741			       <&dmamux1 108 0x400 0x1>;
742			dma-names = "ch1", "up", "trig", "com";
743			status = "disabled";
744
745			pwm {
746				compatible = "st,stm32-pwm";
747				#pwm-cells = <3>;
748				status = "disabled";
749			};
750
751			timer@14 {
752				compatible = "st,stm32h7-timer-trigger";
753				reg = <14>;
754				status = "disabled";
755			};
756		};
757
758		timers16: timer@44007000 {
759			#address-cells = <1>;
760			#size-cells = <0>;
761			compatible = "st,stm32-timers";
762			reg = <0x44007000 0x400>;
763			clocks = <&rcc TIM16_K>;
764			clock-names = "int";
765			dmas = <&dmamux1 109 0x400 0x1>,
766			       <&dmamux1 110 0x400 0x1>;
767			dma-names = "ch1", "up";
768			status = "disabled";
769
770			pwm {
771				compatible = "st,stm32-pwm";
772				#pwm-cells = <3>;
773				status = "disabled";
774			};
775			timer@15 {
776				compatible = "st,stm32h7-timer-trigger";
777				reg = <15>;
778				status = "disabled";
779			};
780		};
781
782		timers17: timer@44008000 {
783			#address-cells = <1>;
784			#size-cells = <0>;
785			compatible = "st,stm32-timers";
786			reg = <0x44008000 0x400>;
787			clocks = <&rcc TIM17_K>;
788			clock-names = "int";
789			dmas = <&dmamux1 111 0x400 0x1>,
790			       <&dmamux1 112 0x400 0x1>;
791			dma-names = "ch1", "up";
792			status = "disabled";
793
794			pwm {
795				compatible = "st,stm32-pwm";
796				#pwm-cells = <3>;
797				status = "disabled";
798			};
799
800			timer@16 {
801				compatible = "st,stm32h7-timer-trigger";
802				reg = <16>;
803				status = "disabled";
804			};
805		};
806
807		spi5: spi@44009000 {
808			#address-cells = <1>;
809			#size-cells = <0>;
810			compatible = "st,stm32h7-spi";
811			reg = <0x44009000 0x400>;
812			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
813			clocks = <&rcc SPI5_K>;
814			resets = <&rcc SPI5_R>;
815			dmas = <&dmamux1 85 0x400 0x05>,
816			       <&dmamux1 86 0x400 0x05>;
817			dma-names = "rx", "tx";
818			status = "disabled";
819		};
820
821		sai1: sai@4400a000 {
822			compatible = "st,stm32h7-sai";
823			#address-cells = <1>;
824			#size-cells = <1>;
825			ranges = <0 0x4400a000 0x400>;
826			reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
827			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
828			resets = <&rcc SAI1_R>;
829			status = "disabled";
830
831			sai1a: audio-controller@4400a004 {
832				#sound-dai-cells = <0>;
833
834				compatible = "st,stm32-sai-sub-a";
835				reg = <0x4 0x20>;
836				clocks = <&rcc SAI1_K>;
837				clock-names = "sai_ck";
838				dmas = <&dmamux1 87 0x400 0x01>;
839				status = "disabled";
840			};
841
842			sai1b: audio-controller@4400a024 {
843				#sound-dai-cells = <0>;
844				compatible = "st,stm32-sai-sub-b";
845				reg = <0x24 0x20>;
846				clocks = <&rcc SAI1_K>;
847				clock-names = "sai_ck";
848				dmas = <&dmamux1 88 0x400 0x01>;
849				status = "disabled";
850			};
851		};
852
853		sai2: sai@4400b000 {
854			compatible = "st,stm32h7-sai";
855			#address-cells = <1>;
856			#size-cells = <1>;
857			ranges = <0 0x4400b000 0x400>;
858			reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
859			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
860			resets = <&rcc SAI2_R>;
861			status = "disabled";
862
863			sai2a: audio-controller@4400b004 {
864				#sound-dai-cells = <0>;
865				compatible = "st,stm32-sai-sub-a";
866				reg = <0x4 0x20>;
867				clocks = <&rcc SAI2_K>;
868				clock-names = "sai_ck";
869				dmas = <&dmamux1 89 0x400 0x01>;
870				status = "disabled";
871			};
872
873			sai2b: audio-controller@4400b024 {
874				#sound-dai-cells = <0>;
875				compatible = "st,stm32-sai-sub-b";
876				reg = <0x24 0x20>;
877				clocks = <&rcc SAI2_K>;
878				clock-names = "sai_ck";
879				dmas = <&dmamux1 90 0x400 0x01>;
880				status = "disabled";
881			};
882		};
883
884		sai3: sai@4400c000 {
885			compatible = "st,stm32h7-sai";
886			#address-cells = <1>;
887			#size-cells = <1>;
888			ranges = <0 0x4400c000 0x400>;
889			reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
890			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
891			resets = <&rcc SAI3_R>;
892			status = "disabled";
893
894			sai3a: audio-controller@4400c004 {
895				#sound-dai-cells = <0>;
896				compatible = "st,stm32-sai-sub-a";
897				reg = <0x04 0x20>;
898				clocks = <&rcc SAI3_K>;
899				clock-names = "sai_ck";
900				dmas = <&dmamux1 113 0x400 0x01>;
901				status = "disabled";
902			};
903
904			sai3b: audio-controller@4400c024 {
905				#sound-dai-cells = <0>;
906				compatible = "st,stm32-sai-sub-b";
907				reg = <0x24 0x20>;
908				clocks = <&rcc SAI3_K>;
909				clock-names = "sai_ck";
910				dmas = <&dmamux1 114 0x400 0x01>;
911				status = "disabled";
912			};
913		};
914
915		dfsdm: dfsdm@4400d000 {
916			compatible = "st,stm32mp1-dfsdm";
917			reg = <0x4400d000 0x800>;
918			clocks = <&rcc DFSDM_K>;
919			clock-names = "dfsdm";
920			#address-cells = <1>;
921			#size-cells = <0>;
922			status = "disabled";
923
924			dfsdm0: filter@0 {
925				compatible = "st,stm32-dfsdm-adc";
926				#io-channel-cells = <1>;
927				reg = <0>;
928				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
929				dmas = <&dmamux1 101 0x400 0x01>;
930				dma-names = "rx";
931				status = "disabled";
932			};
933
934			dfsdm1: filter@1 {
935				compatible = "st,stm32-dfsdm-adc";
936				#io-channel-cells = <1>;
937				reg = <1>;
938				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
939				dmas = <&dmamux1 102 0x400 0x01>;
940				dma-names = "rx";
941				status = "disabled";
942			};
943
944			dfsdm2: filter@2 {
945				compatible = "st,stm32-dfsdm-adc";
946				#io-channel-cells = <1>;
947				reg = <2>;
948				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
949				dmas = <&dmamux1 103 0x400 0x01>;
950				dma-names = "rx";
951				status = "disabled";
952			};
953
954			dfsdm3: filter@3 {
955				compatible = "st,stm32-dfsdm-adc";
956				#io-channel-cells = <1>;
957				reg = <3>;
958				interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
959				dmas = <&dmamux1 104 0x400 0x01>;
960				dma-names = "rx";
961				status = "disabled";
962			};
963
964			dfsdm4: filter@4 {
965				compatible = "st,stm32-dfsdm-adc";
966				#io-channel-cells = <1>;
967				reg = <4>;
968				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
969				dmas = <&dmamux1 91 0x400 0x01>;
970				dma-names = "rx";
971				status = "disabled";
972			};
973
974			dfsdm5: filter@5 {
975				compatible = "st,stm32-dfsdm-adc";
976				#io-channel-cells = <1>;
977				reg = <5>;
978				interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
979				dmas = <&dmamux1 92 0x400 0x01>;
980				dma-names = "rx";
981				status = "disabled";
982			};
983		};
984
985		dma1: dma-controller@48000000 {
986			compatible = "st,stm32-dma";
987			reg = <0x48000000 0x400>;
988			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
989				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
990				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
991				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
992				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
993				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
994				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
995				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
996			clocks = <&rcc DMA1>;
997			resets = <&rcc DMA1_R>;
998			#dma-cells = <4>;
999			st,mem2mem;
1000			dma-requests = <8>;
1001		};
1002
1003		dma2: dma-controller@48001000 {
1004			compatible = "st,stm32-dma";
1005			reg = <0x48001000 0x400>;
1006			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1007				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1008				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1009				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1010				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1011				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1012				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1013				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1014			clocks = <&rcc DMA2>;
1015			resets = <&rcc DMA2_R>;
1016			#dma-cells = <4>;
1017			st,mem2mem;
1018			dma-requests = <8>;
1019		};
1020
1021		dmamux1: dma-router@48002000 {
1022			compatible = "st,stm32h7-dmamux";
1023			reg = <0x48002000 0x40>;
1024			#dma-cells = <3>;
1025			dma-requests = <128>;
1026			dma-masters = <&dma1 &dma2>;
1027			dma-channels = <16>;
1028			clocks = <&rcc DMAMUX>;
1029			resets = <&rcc DMAMUX_R>;
1030		};
1031
1032		adc: adc@48003000 {
1033			compatible = "st,stm32mp1-adc-core";
1034			reg = <0x48003000 0x400>;
1035			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1036				     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1037			clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1038			clock-names = "bus", "adc";
1039			interrupt-controller;
1040			st,syscfg = <&syscfg>;
1041			#interrupt-cells = <1>;
1042			#address-cells = <1>;
1043			#size-cells = <0>;
1044			status = "disabled";
1045
1046			adc1: adc@0 {
1047				compatible = "st,stm32mp1-adc";
1048				#io-channel-cells = <1>;
1049				reg = <0x0>;
1050				interrupt-parent = <&adc>;
1051				interrupts = <0>;
1052				dmas = <&dmamux1 9 0x400 0x01>;
1053				dma-names = "rx";
1054				status = "disabled";
1055			};
1056
1057			adc2: adc@100 {
1058				compatible = "st,stm32mp1-adc";
1059				#io-channel-cells = <1>;
1060				reg = <0x100>;
1061				interrupt-parent = <&adc>;
1062				interrupts = <1>;
1063				dmas = <&dmamux1 10 0x400 0x01>;
1064				dma-names = "rx";
1065				status = "disabled";
1066			};
1067		};
1068
1069		sdmmc3: mmc@48004000 {
1070			compatible = "arm,pl18x", "arm,primecell";
1071			arm,primecell-periphid = <0x00253180>;
1072			reg = <0x48004000 0x400>;
1073			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1074			interrupt-names = "cmd_irq";
1075			clocks = <&rcc SDMMC3_K>;
1076			clock-names = "apb_pclk";
1077			resets = <&rcc SDMMC3_R>;
1078			cap-sd-highspeed;
1079			cap-mmc-highspeed;
1080			max-frequency = <120000000>;
1081			status = "disabled";
1082		};
1083
1084		usbotg_hs: usb-otg@49000000 {
1085			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1086			reg = <0x49000000 0x10000>;
1087			clocks = <&rcc USBO_K>;
1088			clock-names = "otg";
1089			resets = <&rcc USBO_R>;
1090			reset-names = "dwc2";
1091			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1092			g-rx-fifo-size = <512>;
1093			g-np-tx-fifo-size = <32>;
1094			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
1095			dr_mode = "otg";
1096			otg-rev = <0x200>;
1097			usb33d-supply = <&usb33>;
1098			status = "disabled";
1099		};
1100
1101		ipcc: mailbox@4c001000 {
1102			compatible = "st,stm32mp1-ipcc";
1103			#mbox-cells = <1>;
1104			reg = <0x4c001000 0x400>;
1105			st,proc-id = <0>;
1106			interrupts-extended =
1107				<&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1108				<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1109				<&exti 61 1>;
1110			interrupt-names = "rx", "tx", "wakeup";
1111			clocks = <&rcc IPCC>;
1112			wakeup-source;
1113			status = "disabled";
1114		};
1115
1116		dcmi: dcmi@4c006000 {
1117			compatible = "st,stm32-dcmi";
1118			reg = <0x4c006000 0x400>;
1119			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1120			resets = <&rcc CAMITF_R>;
1121			clocks = <&rcc DCMI>;
1122			clock-names = "mclk";
1123			dmas = <&dmamux1 75 0x400 0x01>;
1124			dma-names = "tx";
1125			status = "disabled";
1126		};
1127
1128		rcc: rcc@50000000 {
1129			compatible = "st,stm32mp1-rcc", "syscon";
1130			reg = <0x50000000 0x1000>;
1131			#clock-cells = <1>;
1132			#reset-cells = <1>;
1133		};
1134
1135		pwr_regulators: pwr@50001000 {
1136			compatible = "st,stm32mp1,pwr-reg";
1137			reg = <0x50001000 0x10>;
1138
1139			reg11: reg11 {
1140				regulator-name = "reg11";
1141				regulator-min-microvolt = <1100000>;
1142				regulator-max-microvolt = <1100000>;
1143			};
1144
1145			reg18: reg18 {
1146				regulator-name = "reg18";
1147				regulator-min-microvolt = <1800000>;
1148				regulator-max-microvolt = <1800000>;
1149			};
1150
1151			usb33: usb33 {
1152				regulator-name = "usb33";
1153				regulator-min-microvolt = <3300000>;
1154				regulator-max-microvolt = <3300000>;
1155			};
1156		};
1157
1158		pwr_mcu: pwr_mcu@50001014 {
1159			compatible = "st,stm32mp151-pwr-mcu", "syscon";
1160			reg = <0x50001014 0x4>;
1161		};
1162
1163		exti: interrupt-controller@5000d000 {
1164			compatible = "st,stm32mp1-exti", "syscon";
1165			interrupt-controller;
1166			#interrupt-cells = <2>;
1167			reg = <0x5000d000 0x400>;
1168		};
1169
1170		syscfg: syscon@50020000 {
1171			compatible = "st,stm32mp157-syscfg", "syscon";
1172			reg = <0x50020000 0x400>;
1173			clocks = <&rcc SYSCFG>;
1174		};
1175
1176		lptimer2: timer@50021000 {
1177			#address-cells = <1>;
1178			#size-cells = <0>;
1179			compatible = "st,stm32-lptimer";
1180			reg = <0x50021000 0x400>;
1181			interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
1182			clocks = <&rcc LPTIM2_K>;
1183			clock-names = "mux";
1184			wakeup-source;
1185			status = "disabled";
1186
1187			pwm {
1188				compatible = "st,stm32-pwm-lp";
1189				#pwm-cells = <3>;
1190				status = "disabled";
1191			};
1192
1193			trigger@1 {
1194				compatible = "st,stm32-lptimer-trigger";
1195				reg = <1>;
1196				status = "disabled";
1197			};
1198
1199			counter {
1200				compatible = "st,stm32-lptimer-counter";
1201				status = "disabled";
1202			};
1203		};
1204
1205		lptimer3: timer@50022000 {
1206			#address-cells = <1>;
1207			#size-cells = <0>;
1208			compatible = "st,stm32-lptimer";
1209			reg = <0x50022000 0x400>;
1210			interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
1211			clocks = <&rcc LPTIM3_K>;
1212			clock-names = "mux";
1213			wakeup-source;
1214			status = "disabled";
1215
1216			pwm {
1217				compatible = "st,stm32-pwm-lp";
1218				#pwm-cells = <3>;
1219				status = "disabled";
1220			};
1221
1222			trigger@2 {
1223				compatible = "st,stm32-lptimer-trigger";
1224				reg = <2>;
1225				status = "disabled";
1226			};
1227		};
1228
1229		lptimer4: timer@50023000 {
1230			compatible = "st,stm32-lptimer";
1231			reg = <0x50023000 0x400>;
1232			interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
1233			clocks = <&rcc LPTIM4_K>;
1234			clock-names = "mux";
1235			wakeup-source;
1236			status = "disabled";
1237
1238			pwm {
1239				compatible = "st,stm32-pwm-lp";
1240				#pwm-cells = <3>;
1241				status = "disabled";
1242			};
1243		};
1244
1245		lptimer5: timer@50024000 {
1246			compatible = "st,stm32-lptimer";
1247			reg = <0x50024000 0x400>;
1248			interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
1249			clocks = <&rcc LPTIM5_K>;
1250			clock-names = "mux";
1251			wakeup-source;
1252			status = "disabled";
1253
1254			pwm {
1255				compatible = "st,stm32-pwm-lp";
1256				#pwm-cells = <3>;
1257				status = "disabled";
1258			};
1259		};
1260
1261		vrefbuf: vrefbuf@50025000 {
1262			compatible = "st,stm32-vrefbuf";
1263			reg = <0x50025000 0x8>;
1264			regulator-min-microvolt = <1500000>;
1265			regulator-max-microvolt = <2500000>;
1266			clocks = <&rcc VREF>;
1267			status = "disabled";
1268		};
1269
1270		sai4: sai@50027000 {
1271			compatible = "st,stm32h7-sai";
1272			#address-cells = <1>;
1273			#size-cells = <1>;
1274			ranges = <0 0x50027000 0x400>;
1275			reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1276			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1277			resets = <&rcc SAI4_R>;
1278			status = "disabled";
1279
1280			sai4a: audio-controller@50027004 {
1281				#sound-dai-cells = <0>;
1282				compatible = "st,stm32-sai-sub-a";
1283				reg = <0x04 0x20>;
1284				clocks = <&rcc SAI4_K>;
1285				clock-names = "sai_ck";
1286				dmas = <&dmamux1 99 0x400 0x01>;
1287				status = "disabled";
1288			};
1289
1290			sai4b: audio-controller@50027024 {
1291				#sound-dai-cells = <0>;
1292				compatible = "st,stm32-sai-sub-b";
1293				reg = <0x24 0x20>;
1294				clocks = <&rcc SAI4_K>;
1295				clock-names = "sai_ck";
1296				dmas = <&dmamux1 100 0x400 0x01>;
1297				status = "disabled";
1298			};
1299		};
1300
1301		dts: thermal@50028000 {
1302			compatible = "st,stm32-thermal";
1303			reg = <0x50028000 0x100>;
1304			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1305			clocks = <&rcc TMPSENS>;
1306			clock-names = "pclk";
1307			#thermal-sensor-cells = <0>;
1308			status = "disabled";
1309		};
1310
1311		hash1: hash@54002000 {
1312			compatible = "st,stm32f756-hash";
1313			reg = <0x54002000 0x400>;
1314			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1315			clocks = <&rcc HASH1>;
1316			resets = <&rcc HASH1_R>;
1317			dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
1318			dma-names = "in";
1319			dma-maxburst = <2>;
1320			status = "disabled";
1321		};
1322
1323		rng1: rng@54003000 {
1324			compatible = "st,stm32-rng";
1325			reg = <0x54003000 0x400>;
1326			clocks = <&rcc RNG1_K>;
1327			resets = <&rcc RNG1_R>;
1328			status = "disabled";
1329		};
1330
1331		mdma1: dma-controller@58000000 {
1332			compatible = "st,stm32h7-mdma";
1333			reg = <0x58000000 0x1000>;
1334			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1335			clocks = <&rcc MDMA>;
1336			resets = <&rcc MDMA_R>;
1337			#dma-cells = <5>;
1338			dma-channels = <32>;
1339			dma-requests = <48>;
1340		};
1341
1342		fmc: memory-controller@58002000 {
1343			#address-cells = <2>;
1344			#size-cells = <1>;
1345			compatible = "st,stm32mp1-fmc2-ebi";
1346			reg = <0x58002000 0x1000>;
1347			clocks = <&rcc FMC_K>;
1348			resets = <&rcc FMC_R>;
1349			status = "disabled";
1350
1351			ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
1352				 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
1353				 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
1354				 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
1355				 <4 0 0x80000000 0x10000000>; /* NAND */
1356
1357			nand-controller@4,0 {
1358				#address-cells = <1>;
1359				#size-cells = <0>;
1360				compatible = "st,stm32mp1-fmc2-nfc";
1361				reg = <4 0x00000000 0x1000>,
1362				      <4 0x08010000 0x1000>,
1363				      <4 0x08020000 0x1000>,
1364				      <4 0x01000000 0x1000>,
1365				      <4 0x09010000 0x1000>,
1366				      <4 0x09020000 0x1000>;
1367				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1368				dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
1369				       <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
1370				       <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
1371				dma-names = "tx", "rx", "ecc";
1372				status = "disabled";
1373			};
1374		};
1375
1376		qspi: spi@58003000 {
1377			compatible = "st,stm32f469-qspi";
1378			reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1379			reg-names = "qspi", "qspi_mm";
1380			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1381			dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
1382			       <&mdma1 22 0x2 0x10100008 0x0 0x0>;
1383			dma-names = "tx", "rx";
1384			clocks = <&rcc QSPI_K>;
1385			resets = <&rcc QSPI_R>;
1386			#address-cells = <1>;
1387			#size-cells = <0>;
1388			status = "disabled";
1389		};
1390
1391		sdmmc1: mmc@58005000 {
1392			compatible = "arm,pl18x", "arm,primecell";
1393			arm,primecell-periphid = <0x00253180>;
1394			reg = <0x58005000 0x1000>;
1395			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1396			interrupt-names = "cmd_irq";
1397			clocks = <&rcc SDMMC1_K>;
1398			clock-names = "apb_pclk";
1399			resets = <&rcc SDMMC1_R>;
1400			cap-sd-highspeed;
1401			cap-mmc-highspeed;
1402			max-frequency = <120000000>;
1403			status = "disabled";
1404		};
1405
1406		sdmmc2: mmc@58007000 {
1407			compatible = "arm,pl18x", "arm,primecell";
1408			arm,primecell-periphid = <0x00253180>;
1409			reg = <0x58007000 0x1000>;
1410			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1411			interrupt-names = "cmd_irq";
1412			clocks = <&rcc SDMMC2_K>;
1413			clock-names = "apb_pclk";
1414			resets = <&rcc SDMMC2_R>;
1415			cap-sd-highspeed;
1416			cap-mmc-highspeed;
1417			max-frequency = <120000000>;
1418			status = "disabled";
1419		};
1420
1421		crc1: crc@58009000 {
1422			compatible = "st,stm32f7-crc";
1423			reg = <0x58009000 0x400>;
1424			clocks = <&rcc CRC1>;
1425			status = "disabled";
1426		};
1427
1428		ethernet0: ethernet@5800a000 {
1429			compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1430			reg = <0x5800a000 0x2000>;
1431			reg-names = "stmmaceth";
1432			interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1433			interrupt-names = "macirq";
1434			clock-names = "stmmaceth",
1435				      "mac-clk-tx",
1436				      "mac-clk-rx",
1437				      "eth-ck",
1438				      "ptp_ref",
1439				      "ethstp";
1440			clocks = <&rcc ETHMAC>,
1441				 <&rcc ETHTX>,
1442				 <&rcc ETHRX>,
1443				 <&rcc ETHCK_K>,
1444				 <&rcc ETHPTP_K>,
1445				 <&rcc ETHSTP>;
1446			st,syscon = <&syscfg 0x4>;
1447			snps,mixed-burst;
1448			snps,pbl = <2>;
1449			snps,en-tx-lpi-clockgating;
1450			snps,axi-config = <&stmmac_axi_config_0>;
1451			snps,tso;
1452			status = "disabled";
1453
1454			stmmac_axi_config_0: stmmac-axi-config {
1455				snps,wr_osr_lmt = <0x7>;
1456				snps,rd_osr_lmt = <0x7>;
1457				snps,blen = <0 0 0 0 16 8 4>;
1458			};
1459		};
1460
1461		usbh_ohci: usb@5800c000 {
1462			compatible = "generic-ohci";
1463			reg = <0x5800c000 0x1000>;
1464			clocks = <&rcc USBH>, <&usbphyc>;
1465			resets = <&rcc USBH_R>;
1466			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1467			status = "disabled";
1468		};
1469
1470		usbh_ehci: usb@5800d000 {
1471			compatible = "generic-ehci";
1472			reg = <0x5800d000 0x1000>;
1473			clocks = <&rcc USBH>;
1474			resets = <&rcc USBH_R>;
1475			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1476			companion = <&usbh_ohci>;
1477			status = "disabled";
1478		};
1479
1480		ltdc: display-controller@5a001000 {
1481			compatible = "st,stm32-ltdc";
1482			reg = <0x5a001000 0x400>;
1483			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1484				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1485			clocks = <&rcc LTDC_PX>;
1486			clock-names = "lcd";
1487			resets = <&rcc LTDC_R>;
1488			status = "disabled";
1489
1490			port {
1491				#address-cells = <1>;
1492				#size-cells = <0>;
1493			};
1494		};
1495
1496		iwdg2: watchdog@5a002000 {
1497			compatible = "st,stm32mp1-iwdg";
1498			reg = <0x5a002000 0x400>;
1499			clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1500			clock-names = "pclk", "lsi";
1501			status = "disabled";
1502		};
1503
1504		usbphyc: usbphyc@5a006000 {
1505			#address-cells = <1>;
1506			#size-cells = <0>;
1507			#clock-cells = <0>;
1508			compatible = "st,stm32mp1-usbphyc";
1509			reg = <0x5a006000 0x1000>;
1510			clocks = <&rcc USBPHY_K>;
1511			resets = <&rcc USBPHY_R>;
1512			vdda1v1-supply = <&reg11>;
1513			vdda1v8-supply = <&reg18>;
1514			status = "disabled";
1515
1516			usbphyc_port0: usb-phy@0 {
1517				#phy-cells = <0>;
1518				reg = <0>;
1519			};
1520
1521			usbphyc_port1: usb-phy@1 {
1522				#phy-cells = <1>;
1523				reg = <1>;
1524			};
1525		};
1526
1527		usart1: serial@5c000000 {
1528			compatible = "st,stm32h7-uart";
1529			reg = <0x5c000000 0x400>;
1530			interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
1531			clocks = <&rcc USART1_K>;
1532			wakeup-source;
1533			status = "disabled";
1534		};
1535
1536		spi6: spi@5c001000 {
1537			#address-cells = <1>;
1538			#size-cells = <0>;
1539			compatible = "st,stm32h7-spi";
1540			reg = <0x5c001000 0x400>;
1541			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1542			clocks = <&rcc SPI6_K>;
1543			resets = <&rcc SPI6_R>;
1544			dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1545			       <&mdma1 35 0x0 0x40002 0x0 0x0>;
1546			dma-names = "rx", "tx";
1547			status = "disabled";
1548		};
1549
1550		i2c4: i2c@5c002000 {
1551			compatible = "st,stm32mp15-i2c";
1552			reg = <0x5c002000 0x400>;
1553			interrupt-names = "event", "error";
1554			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1555				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1556			clocks = <&rcc I2C4_K>;
1557			resets = <&rcc I2C4_R>;
1558			#address-cells = <1>;
1559			#size-cells = <0>;
1560			st,syscfg-fmp = <&syscfg 0x4 0x8>;
1561			wakeup-source;
1562			i2c-analog-filter;
1563			status = "disabled";
1564		};
1565
1566		rtc: rtc@5c004000 {
1567			compatible = "st,stm32mp1-rtc";
1568			reg = <0x5c004000 0x400>;
1569			clocks = <&rcc RTCAPB>, <&rcc RTC>;
1570			clock-names = "pclk", "rtc_ck";
1571			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1572			status = "disabled";
1573		};
1574
1575		bsec: efuse@5c005000 {
1576			compatible = "st,stm32mp15-bsec";
1577			reg = <0x5c005000 0x400>;
1578			#address-cells = <1>;
1579			#size-cells = <1>;
1580			ts_cal1: calib@5c {
1581				reg = <0x5c 0x2>;
1582			};
1583			ts_cal2: calib@5e {
1584				reg = <0x5e 0x2>;
1585			};
1586		};
1587
1588		i2c6: i2c@5c009000 {
1589			compatible = "st,stm32mp15-i2c";
1590			reg = <0x5c009000 0x400>;
1591			interrupt-names = "event", "error";
1592			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1593				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1594			clocks = <&rcc I2C6_K>;
1595			resets = <&rcc I2C6_R>;
1596			#address-cells = <1>;
1597			#size-cells = <0>;
1598			st,syscfg-fmp = <&syscfg 0x4 0x20>;
1599			wakeup-source;
1600			i2c-analog-filter;
1601			status = "disabled";
1602		};
1603
1604		tamp: tamp@5c00a000 {
1605			compatible = "st,stm32-tamp", "syscon", "simple-mfd";
1606			reg = <0x5c00a000 0x400>;
1607		};
1608
1609		/*
1610		 * Break node order to solve dependency probe issue between
1611		 * pinctrl and exti.
1612		 */
1613		pinctrl: pin-controller@50002000 {
1614			#address-cells = <1>;
1615			#size-cells = <1>;
1616			compatible = "st,stm32mp157-pinctrl";
1617			ranges = <0 0x50002000 0xa400>;
1618			interrupt-parent = <&exti>;
1619			st,syscfg = <&exti 0x60 0xff>;
1620			pins-are-numbered;
1621
1622			gpioa: gpio@50002000 {
1623				gpio-controller;
1624				#gpio-cells = <2>;
1625				interrupt-controller;
1626				#interrupt-cells = <2>;
1627				reg = <0x0 0x400>;
1628				clocks = <&rcc GPIOA>;
1629				st,bank-name = "GPIOA";
1630				status = "disabled";
1631			};
1632
1633			gpiob: gpio@50003000 {
1634				gpio-controller;
1635				#gpio-cells = <2>;
1636				interrupt-controller;
1637				#interrupt-cells = <2>;
1638				reg = <0x1000 0x400>;
1639				clocks = <&rcc GPIOB>;
1640				st,bank-name = "GPIOB";
1641				status = "disabled";
1642			};
1643
1644			gpioc: gpio@50004000 {
1645				gpio-controller;
1646				#gpio-cells = <2>;
1647				interrupt-controller;
1648				#interrupt-cells = <2>;
1649				reg = <0x2000 0x400>;
1650				clocks = <&rcc GPIOC>;
1651				st,bank-name = "GPIOC";
1652				status = "disabled";
1653			};
1654
1655			gpiod: gpio@50005000 {
1656				gpio-controller;
1657				#gpio-cells = <2>;
1658				interrupt-controller;
1659				#interrupt-cells = <2>;
1660				reg = <0x3000 0x400>;
1661				clocks = <&rcc GPIOD>;
1662				st,bank-name = "GPIOD";
1663				status = "disabled";
1664			};
1665
1666			gpioe: gpio@50006000 {
1667				gpio-controller;
1668				#gpio-cells = <2>;
1669				interrupt-controller;
1670				#interrupt-cells = <2>;
1671				reg = <0x4000 0x400>;
1672				clocks = <&rcc GPIOE>;
1673				st,bank-name = "GPIOE";
1674				status = "disabled";
1675			};
1676
1677			gpiof: gpio@50007000 {
1678				gpio-controller;
1679				#gpio-cells = <2>;
1680				interrupt-controller;
1681				#interrupt-cells = <2>;
1682				reg = <0x5000 0x400>;
1683				clocks = <&rcc GPIOF>;
1684				st,bank-name = "GPIOF";
1685				status = "disabled";
1686			};
1687
1688			gpiog: gpio@50008000 {
1689				gpio-controller;
1690				#gpio-cells = <2>;
1691				interrupt-controller;
1692				#interrupt-cells = <2>;
1693				reg = <0x6000 0x400>;
1694				clocks = <&rcc GPIOG>;
1695				st,bank-name = "GPIOG";
1696				status = "disabled";
1697			};
1698
1699			gpioh: gpio@50009000 {
1700				gpio-controller;
1701				#gpio-cells = <2>;
1702				interrupt-controller;
1703				#interrupt-cells = <2>;
1704				reg = <0x7000 0x400>;
1705				clocks = <&rcc GPIOH>;
1706				st,bank-name = "GPIOH";
1707				status = "disabled";
1708			};
1709
1710			gpioi: gpio@5000a000 {
1711				gpio-controller;
1712				#gpio-cells = <2>;
1713				interrupt-controller;
1714				#interrupt-cells = <2>;
1715				reg = <0x8000 0x400>;
1716				clocks = <&rcc GPIOI>;
1717				st,bank-name = "GPIOI";
1718				status = "disabled";
1719			};
1720
1721			gpioj: gpio@5000b000 {
1722				gpio-controller;
1723				#gpio-cells = <2>;
1724				interrupt-controller;
1725				#interrupt-cells = <2>;
1726				reg = <0x9000 0x400>;
1727				clocks = <&rcc GPIOJ>;
1728				st,bank-name = "GPIOJ";
1729				status = "disabled";
1730			};
1731
1732			gpiok: gpio@5000c000 {
1733				gpio-controller;
1734				#gpio-cells = <2>;
1735				interrupt-controller;
1736				#interrupt-cells = <2>;
1737				reg = <0xa000 0x400>;
1738				clocks = <&rcc GPIOK>;
1739				st,bank-name = "GPIOK";
1740				status = "disabled";
1741			};
1742		};
1743
1744		pinctrl_z: pin-controller-z@54004000 {
1745			#address-cells = <1>;
1746			#size-cells = <1>;
1747			compatible = "st,stm32mp157-z-pinctrl";
1748			ranges = <0 0x54004000 0x400>;
1749			pins-are-numbered;
1750			interrupt-parent = <&exti>;
1751			st,syscfg = <&exti 0x60 0xff>;
1752
1753			gpioz: gpio@54004000 {
1754				gpio-controller;
1755				#gpio-cells = <2>;
1756				interrupt-controller;
1757				#interrupt-cells = <2>;
1758				reg = <0 0x400>;
1759				clocks = <&rcc GPIOZ>;
1760				st,bank-name = "GPIOZ";
1761				st,bank-ioport = <11>;
1762				status = "disabled";
1763			};
1764		};
1765	};
1766
1767	mlahb: ahb {
1768		compatible = "st,mlahb", "simple-bus";
1769		#address-cells = <1>;
1770		#size-cells = <1>;
1771		ranges;
1772		dma-ranges = <0x00000000 0x38000000 0x10000>,
1773			     <0x10000000 0x10000000 0x60000>,
1774			     <0x30000000 0x30000000 0x60000>;
1775
1776		m4_rproc: m4@10000000 {
1777			compatible = "st,stm32mp1-m4";
1778			reg = <0x10000000 0x40000>,
1779			      <0x30000000 0x40000>,
1780			      <0x38000000 0x10000>;
1781			resets = <&rcc MCU_R>;
1782			st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1783			st,syscfg-tz = <&rcc 0x000 0x1>;
1784			st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
1785			st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
1786			st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
1787			status = "disabled";
1788		};
1789	};
1790};
1791