1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra114-car.h>
3#include <dt-bindings/gpio/tegra-gpio.h>
4#include <dt-bindings/memory/tegra114-mc.h>
5#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/soc/tegra-pmc.h>
8
9/ {
10	compatible = "nvidia,tegra114";
11	interrupt-parent = <&lic>;
12	#address-cells = <1>;
13	#size-cells = <1>;
14
15	memory@80000000 {
16		device_type = "memory";
17		reg = <0x80000000 0x0>;
18	};
19
20	host1x@50000000 {
21		compatible = "nvidia,tegra114-host1x";
22		reg = <0x50000000 0x00028000>;
23		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
24			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
25		interrupt-names = "syncpt", "host1x";
26		clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
27		clock-names = "host1x";
28		resets = <&tegra_car 28>;
29		reset-names = "host1x";
30		iommus = <&mc TEGRA_SWGROUP_HC>;
31
32		#address-cells = <1>;
33		#size-cells = <1>;
34
35		ranges = <0x54000000 0x54000000 0x01000000>;
36
37		gr2d@54140000 {
38			compatible = "nvidia,tegra114-gr2d";
39			reg = <0x54140000 0x00040000>;
40			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
41			clocks = <&tegra_car TEGRA114_CLK_GR2D>;
42			resets = <&tegra_car 21>;
43			reset-names = "2d";
44
45			iommus = <&mc TEGRA_SWGROUP_G2>;
46		};
47
48		gr3d@54180000 {
49			compatible = "nvidia,tegra114-gr3d";
50			reg = <0x54180000 0x00040000>;
51			clocks = <&tegra_car TEGRA114_CLK_GR3D>;
52			resets = <&tegra_car 24>;
53			reset-names = "3d";
54
55			iommus = <&mc TEGRA_SWGROUP_NV>;
56		};
57
58		dc@54200000 {
59			compatible = "nvidia,tegra114-dc";
60			reg = <0x54200000 0x00040000>;
61			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
62			clocks = <&tegra_car TEGRA114_CLK_DISP1>,
63				 <&tegra_car TEGRA114_CLK_PLL_P>;
64			clock-names = "dc", "parent";
65			resets = <&tegra_car 27>;
66			reset-names = "dc";
67
68			iommus = <&mc TEGRA_SWGROUP_DC>;
69
70			nvidia,head = <0>;
71
72			rgb {
73				status = "disabled";
74			};
75		};
76
77		dc@54240000 {
78			compatible = "nvidia,tegra114-dc";
79			reg = <0x54240000 0x00040000>;
80			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
81			clocks = <&tegra_car TEGRA114_CLK_DISP2>,
82				 <&tegra_car TEGRA114_CLK_PLL_P>;
83			clock-names = "dc", "parent";
84			resets = <&tegra_car 26>;
85			reset-names = "dc";
86
87			iommus = <&mc TEGRA_SWGROUP_DCB>;
88
89			nvidia,head = <1>;
90
91			rgb {
92				status = "disabled";
93			};
94		};
95
96		hdmi@54280000 {
97			compatible = "nvidia,tegra114-hdmi";
98			reg = <0x54280000 0x00040000>;
99			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
100			clocks = <&tegra_car TEGRA114_CLK_HDMI>,
101				 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
102			clock-names = "hdmi", "parent";
103			resets = <&tegra_car 51>;
104			reset-names = "hdmi";
105			status = "disabled";
106		};
107
108		dsi@54300000 {
109			compatible = "nvidia,tegra114-dsi";
110			reg = <0x54300000 0x00040000>;
111			clocks = <&tegra_car TEGRA114_CLK_DSIA>,
112				 <&tegra_car TEGRA114_CLK_DSIALP>,
113				 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
114			clock-names = "dsi", "lp", "parent";
115			resets = <&tegra_car 48>;
116			reset-names = "dsi";
117			nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
118			status = "disabled";
119
120			#address-cells = <1>;
121			#size-cells = <0>;
122		};
123
124		dsi@54400000 {
125			compatible = "nvidia,tegra114-dsi";
126			reg = <0x54400000 0x00040000>;
127			clocks = <&tegra_car TEGRA114_CLK_DSIB>,
128				 <&tegra_car TEGRA114_CLK_DSIBLP>,
129				 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
130			clock-names = "dsi", "lp", "parent";
131			resets = <&tegra_car 82>;
132			reset-names = "dsi";
133			nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
134			status = "disabled";
135
136			#address-cells = <1>;
137			#size-cells = <0>;
138		};
139	};
140
141	gic: interrupt-controller@50041000 {
142		compatible = "arm,cortex-a15-gic";
143		#interrupt-cells = <3>;
144		interrupt-controller;
145		reg = <0x50041000 0x1000>,
146		      <0x50042000 0x1000>,
147		      <0x50044000 0x2000>,
148		      <0x50046000 0x2000>;
149		interrupts = <GIC_PPI 9
150			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
151		interrupt-parent = <&gic>;
152	};
153
154	lic: interrupt-controller@60004000 {
155		compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
156		reg = <0x60004000 0x100>,
157		      <0x60004100 0x50>,
158		      <0x60004200 0x50>,
159		      <0x60004300 0x50>,
160		      <0x60004400 0x50>;
161		interrupt-controller;
162		#interrupt-cells = <3>;
163		interrupt-parent = <&gic>;
164	};
165
166	timer@60005000 {
167		compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
168		reg = <0x60005000 0x400>;
169		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
170			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
171			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
172			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
173			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
174			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
175		clocks = <&tegra_car TEGRA114_CLK_TIMER>;
176	};
177
178	tegra_car: clock@60006000 {
179		compatible = "nvidia,tegra114-car";
180		reg = <0x60006000 0x1000>;
181		#clock-cells = <1>;
182		#reset-cells = <1>;
183	};
184
185	flow-controller@60007000 {
186		compatible = "nvidia,tegra114-flowctrl";
187		reg = <0x60007000 0x1000>;
188	};
189
190	apbdma: dma@6000a000 {
191		compatible = "nvidia,tegra114-apbdma";
192		reg = <0x6000a000 0x1400>;
193		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
194			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
195			     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
196			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
197			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
198			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
199			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
200			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
201			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
202			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
203			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
204			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
205			     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
206			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
207			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
208			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
209			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
210			     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
211			     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
212			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
213			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
214			     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
215			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
216			     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
217			     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
218			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
219			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
220			     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
221			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
222			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
223			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
224			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
225		clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
226		resets = <&tegra_car 34>;
227		reset-names = "dma";
228		#dma-cells = <1>;
229	};
230
231	ahb: ahb@6000c000 {
232		compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
233		reg = <0x6000c000 0x150>;
234	};
235
236	gpio: gpio@6000d000 {
237		compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
238		reg = <0x6000d000 0x1000>;
239		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
240			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
241			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
242			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
243			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
244			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
245			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
246			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
247		#gpio-cells = <2>;
248		gpio-controller;
249		#interrupt-cells = <2>;
250		interrupt-controller;
251		/*
252		gpio-ranges = <&pinmux 0 0 246>;
253		*/
254	};
255
256	apbmisc@70000800 {
257		compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
258		reg = <0x70000800 0x64>, /* Chip revision */
259		      <0x70000008 0x04>; /* Strapping options */
260	};
261
262	pinmux: pinmux@70000868 {
263		compatible = "nvidia,tegra114-pinmux";
264		reg = <0x70000868 0x148>, /* Pad control registers */
265		      <0x70003000 0x40c>; /* Mux registers */
266	};
267
268	/*
269	 * There are two serial driver i.e. 8250 based simple serial
270	 * driver and APB DMA based serial driver for higher baudrate
271	 * and performace. To enable the 8250 based driver, the compatible
272	 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
273	 * the APB DMA based serial driver, the compatible is
274	 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
275	 */
276	uarta: serial@70006000 {
277		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
278		reg = <0x70006000 0x40>;
279		reg-shift = <2>;
280		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
281		clocks = <&tegra_car TEGRA114_CLK_UARTA>;
282		resets = <&tegra_car 6>;
283		reset-names = "serial";
284		dmas = <&apbdma 8>, <&apbdma 8>;
285		dma-names = "rx", "tx";
286		status = "disabled";
287	};
288
289	uartb: serial@70006040 {
290		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
291		reg = <0x70006040 0x40>;
292		reg-shift = <2>;
293		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
294		clocks = <&tegra_car TEGRA114_CLK_UARTB>;
295		resets = <&tegra_car 7>;
296		reset-names = "serial";
297		dmas = <&apbdma 9>, <&apbdma 9>;
298		dma-names = "rx", "tx";
299		status = "disabled";
300	};
301
302	uartc: serial@70006200 {
303		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
304		reg = <0x70006200 0x100>;
305		reg-shift = <2>;
306		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
307		clocks = <&tegra_car TEGRA114_CLK_UARTC>;
308		resets = <&tegra_car 55>;
309		reset-names = "serial";
310		dmas = <&apbdma 10>, <&apbdma 10>;
311		dma-names = "rx", "tx";
312		status = "disabled";
313	};
314
315	uartd: serial@70006300 {
316		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
317		reg = <0x70006300 0x100>;
318		reg-shift = <2>;
319		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
320		clocks = <&tegra_car TEGRA114_CLK_UARTD>;
321		resets = <&tegra_car 65>;
322		reset-names = "serial";
323		dmas = <&apbdma 19>, <&apbdma 19>;
324		dma-names = "rx", "tx";
325		status = "disabled";
326	};
327
328	pwm: pwm@7000a000 {
329		compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
330		reg = <0x7000a000 0x100>;
331		#pwm-cells = <2>;
332		clocks = <&tegra_car TEGRA114_CLK_PWM>;
333		resets = <&tegra_car 17>;
334		reset-names = "pwm";
335		status = "disabled";
336	};
337
338	i2c@7000c000 {
339		compatible = "nvidia,tegra114-i2c";
340		reg = <0x7000c000 0x100>;
341		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
342		#address-cells = <1>;
343		#size-cells = <0>;
344		clocks = <&tegra_car TEGRA114_CLK_I2C1>;
345		clock-names = "div-clk";
346		resets = <&tegra_car 12>;
347		reset-names = "i2c";
348		dmas = <&apbdma 21>, <&apbdma 21>;
349		dma-names = "rx", "tx";
350		status = "disabled";
351	};
352
353	i2c@7000c400 {
354		compatible = "nvidia,tegra114-i2c";
355		reg = <0x7000c400 0x100>;
356		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
357		#address-cells = <1>;
358		#size-cells = <0>;
359		clocks = <&tegra_car TEGRA114_CLK_I2C2>;
360		clock-names = "div-clk";
361		resets = <&tegra_car 54>;
362		reset-names = "i2c";
363		dmas = <&apbdma 22>, <&apbdma 22>;
364		dma-names = "rx", "tx";
365		status = "disabled";
366	};
367
368	i2c@7000c500 {
369		compatible = "nvidia,tegra114-i2c";
370		reg = <0x7000c500 0x100>;
371		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
372		#address-cells = <1>;
373		#size-cells = <0>;
374		clocks = <&tegra_car TEGRA114_CLK_I2C3>;
375		clock-names = "div-clk";
376		resets = <&tegra_car 67>;
377		reset-names = "i2c";
378		dmas = <&apbdma 23>, <&apbdma 23>;
379		dma-names = "rx", "tx";
380		status = "disabled";
381	};
382
383	i2c@7000c700 {
384		compatible = "nvidia,tegra114-i2c";
385		reg = <0x7000c700 0x100>;
386		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
387		#address-cells = <1>;
388		#size-cells = <0>;
389		clocks = <&tegra_car TEGRA114_CLK_I2C4>;
390		clock-names = "div-clk";
391		resets = <&tegra_car 103>;
392		reset-names = "i2c";
393		dmas = <&apbdma 26>, <&apbdma 26>;
394		dma-names = "rx", "tx";
395		status = "disabled";
396	};
397
398	i2c@7000d000 {
399		compatible = "nvidia,tegra114-i2c";
400		reg = <0x7000d000 0x100>;
401		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
402		#address-cells = <1>;
403		#size-cells = <0>;
404		clocks = <&tegra_car TEGRA114_CLK_I2C5>;
405		clock-names = "div-clk";
406		resets = <&tegra_car 47>;
407		reset-names = "i2c";
408		dmas = <&apbdma 24>, <&apbdma 24>;
409		dma-names = "rx", "tx";
410		status = "disabled";
411	};
412
413	spi@7000d400 {
414		compatible = "nvidia,tegra114-spi";
415		reg = <0x7000d400 0x200>;
416		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
417		#address-cells = <1>;
418		#size-cells = <0>;
419		clocks = <&tegra_car TEGRA114_CLK_SBC1>;
420		clock-names = "spi";
421		resets = <&tegra_car 41>;
422		reset-names = "spi";
423		dmas = <&apbdma 15>, <&apbdma 15>;
424		dma-names = "rx", "tx";
425		status = "disabled";
426	};
427
428	spi@7000d600 {
429		compatible = "nvidia,tegra114-spi";
430		reg = <0x7000d600 0x200>;
431		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
432		#address-cells = <1>;
433		#size-cells = <0>;
434		clocks = <&tegra_car TEGRA114_CLK_SBC2>;
435		clock-names = "spi";
436		resets = <&tegra_car 44>;
437		reset-names = "spi";
438		dmas = <&apbdma 16>, <&apbdma 16>;
439		dma-names = "rx", "tx";
440		status = "disabled";
441	};
442
443	spi@7000d800 {
444		compatible = "nvidia,tegra114-spi";
445		reg = <0x7000d800 0x200>;
446		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
447		#address-cells = <1>;
448		#size-cells = <0>;
449		clocks = <&tegra_car TEGRA114_CLK_SBC3>;
450		clock-names = "spi";
451		resets = <&tegra_car 46>;
452		reset-names = "spi";
453		dmas = <&apbdma 17>, <&apbdma 17>;
454		dma-names = "rx", "tx";
455		status = "disabled";
456	};
457
458	spi@7000da00 {
459		compatible = "nvidia,tegra114-spi";
460		reg = <0x7000da00 0x200>;
461		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
462		#address-cells = <1>;
463		#size-cells = <0>;
464		clocks = <&tegra_car TEGRA114_CLK_SBC4>;
465		clock-names = "spi";
466		resets = <&tegra_car 68>;
467		reset-names = "spi";
468		dmas = <&apbdma 18>, <&apbdma 18>;
469		dma-names = "rx", "tx";
470		status = "disabled";
471	};
472
473	spi@7000dc00 {
474		compatible = "nvidia,tegra114-spi";
475		reg = <0x7000dc00 0x200>;
476		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
477		#address-cells = <1>;
478		#size-cells = <0>;
479		clocks = <&tegra_car TEGRA114_CLK_SBC5>;
480		clock-names = "spi";
481		resets = <&tegra_car 104>;
482		reset-names = "spi";
483		dmas = <&apbdma 27>, <&apbdma 27>;
484		dma-names = "rx", "tx";
485		status = "disabled";
486	};
487
488	spi@7000de00 {
489		compatible = "nvidia,tegra114-spi";
490		reg = <0x7000de00 0x200>;
491		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
492		#address-cells = <1>;
493		#size-cells = <0>;
494		clocks = <&tegra_car TEGRA114_CLK_SBC6>;
495		clock-names = "spi";
496		resets = <&tegra_car 105>;
497		reset-names = "spi";
498		dmas = <&apbdma 28>, <&apbdma 28>;
499		dma-names = "rx", "tx";
500		status = "disabled";
501	};
502
503	rtc@7000e000 {
504		compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
505		reg = <0x7000e000 0x100>;
506		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
507		clocks = <&tegra_car TEGRA114_CLK_RTC>;
508	};
509
510	kbc@7000e200 {
511		compatible = "nvidia,tegra114-kbc";
512		reg = <0x7000e200 0x100>;
513		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
514		clocks = <&tegra_car TEGRA114_CLK_KBC>;
515		resets = <&tegra_car 36>;
516		reset-names = "kbc";
517		status = "disabled";
518	};
519
520	tegra_pmc: pmc@7000e400 {
521		compatible = "nvidia,tegra114-pmc";
522		reg = <0x7000e400 0x400>;
523		clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
524		clock-names = "pclk", "clk32k_in";
525		#clock-cells = <1>;
526	};
527
528	fuse@7000f800 {
529		compatible = "nvidia,tegra114-efuse";
530		reg = <0x7000f800 0x400>;
531		clocks = <&tegra_car TEGRA114_CLK_FUSE>;
532		clock-names = "fuse";
533		resets = <&tegra_car 39>;
534		reset-names = "fuse";
535	};
536
537	mc: memory-controller@70019000 {
538		compatible = "nvidia,tegra114-mc";
539		reg = <0x70019000 0x1000>;
540		clocks = <&tegra_car TEGRA114_CLK_MC>;
541		clock-names = "mc";
542
543		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
544
545		#iommu-cells = <1>;
546	};
547
548	ahub@70080000 {
549		compatible = "nvidia,tegra114-ahub";
550		reg = <0x70080000 0x200>,
551		      <0x70080200 0x100>,
552		      <0x70081000 0x200>;
553		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
554		clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
555			 <&tegra_car TEGRA114_CLK_APBIF>;
556		clock-names = "d_audio", "apbif";
557		resets = <&tegra_car 106>, /* d_audio */
558			 <&tegra_car 107>, /* apbif */
559			 <&tegra_car 30>,  /* i2s0 */
560			 <&tegra_car 11>,  /* i2s1 */
561			 <&tegra_car 18>,  /* i2s2 */
562			 <&tegra_car 101>, /* i2s3 */
563			 <&tegra_car 102>, /* i2s4 */
564			 <&tegra_car 108>, /* dam0 */
565			 <&tegra_car 109>, /* dam1 */
566			 <&tegra_car 110>, /* dam2 */
567			 <&tegra_car 10>,  /* spdif */
568			 <&tegra_car 153>, /* amx */
569			 <&tegra_car 154>; /* adx */
570		reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
571			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
572			      "spdif", "amx", "adx";
573		dmas = <&apbdma 1>, <&apbdma 1>,
574		       <&apbdma 2>, <&apbdma 2>,
575		       <&apbdma 3>, <&apbdma 3>,
576		       <&apbdma 4>, <&apbdma 4>,
577		       <&apbdma 6>, <&apbdma 6>,
578		       <&apbdma 7>, <&apbdma 7>,
579		       <&apbdma 12>, <&apbdma 12>,
580		       <&apbdma 13>, <&apbdma 13>,
581		       <&apbdma 14>, <&apbdma 14>,
582		       <&apbdma 29>, <&apbdma 29>;
583		dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
584			    "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
585			    "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
586			    "rx9", "tx9";
587		ranges;
588		#address-cells = <1>;
589		#size-cells = <1>;
590
591		tegra_i2s0: i2s@70080300 {
592			compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
593			reg = <0x70080300 0x100>;
594			nvidia,ahub-cif-ids = <4 4>;
595			clocks = <&tegra_car TEGRA114_CLK_I2S0>;
596			resets = <&tegra_car 30>;
597			reset-names = "i2s";
598			status = "disabled";
599		};
600
601		tegra_i2s1: i2s@70080400 {
602			compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
603			reg = <0x70080400 0x100>;
604			nvidia,ahub-cif-ids = <5 5>;
605			clocks = <&tegra_car TEGRA114_CLK_I2S1>;
606			resets = <&tegra_car 11>;
607			reset-names = "i2s";
608			status = "disabled";
609		};
610
611		tegra_i2s2: i2s@70080500 {
612			compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
613			reg = <0x70080500 0x100>;
614			nvidia,ahub-cif-ids = <6 6>;
615			clocks = <&tegra_car TEGRA114_CLK_I2S2>;
616			resets = <&tegra_car 18>;
617			reset-names = "i2s";
618			status = "disabled";
619		};
620
621		tegra_i2s3: i2s@70080600 {
622			compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
623			reg = <0x70080600 0x100>;
624			nvidia,ahub-cif-ids = <7 7>;
625			clocks = <&tegra_car TEGRA114_CLK_I2S3>;
626			resets = <&tegra_car 101>;
627			reset-names = "i2s";
628			status = "disabled";
629		};
630
631		tegra_i2s4: i2s@70080700 {
632			compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
633			reg = <0x70080700 0x100>;
634			nvidia,ahub-cif-ids = <8 8>;
635			clocks = <&tegra_car TEGRA114_CLK_I2S4>;
636			resets = <&tegra_car 102>;
637			reset-names = "i2s";
638			status = "disabled";
639		};
640	};
641
642	mipi: mipi@700e3000 {
643		compatible = "nvidia,tegra114-mipi";
644		reg = <0x700e3000 0x100>;
645		clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
646		#nvidia,mipi-calibrate-cells = <1>;
647	};
648
649	mmc@78000000 {
650		compatible = "nvidia,tegra114-sdhci";
651		reg = <0x78000000 0x200>;
652		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
653		clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
654		clock-names = "sdhci";
655		resets = <&tegra_car 14>;
656		reset-names = "sdhci";
657		status = "disabled";
658	};
659
660	mmc@78000200 {
661		compatible = "nvidia,tegra114-sdhci";
662		reg = <0x78000200 0x200>;
663		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
664		clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
665		clock-names = "sdhci";
666		resets = <&tegra_car 9>;
667		reset-names = "sdhci";
668		status = "disabled";
669	};
670
671	mmc@78000400 {
672		compatible = "nvidia,tegra114-sdhci";
673		reg = <0x78000400 0x200>;
674		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
675		clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
676		clock-names = "sdhci";
677		resets = <&tegra_car 69>;
678		reset-names = "sdhci";
679		status = "disabled";
680	};
681
682	mmc@78000600 {
683		compatible = "nvidia,tegra114-sdhci";
684		reg = <0x78000600 0x200>;
685		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
686		clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
687		clock-names = "sdhci";
688		resets = <&tegra_car 15>;
689		reset-names = "sdhci";
690		status = "disabled";
691	};
692
693	usb@7d000000 {
694		compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci";
695		reg = <0x7d000000 0x4000>;
696		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
697		phy_type = "utmi";
698		clocks = <&tegra_car TEGRA114_CLK_USBD>;
699		resets = <&tegra_car 22>;
700		reset-names = "usb";
701		nvidia,phy = <&phy1>;
702		status = "disabled";
703	};
704
705	phy1: usb-phy@7d000000 {
706		compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
707		reg = <0x7d000000 0x4000>,
708		      <0x7d000000 0x4000>;
709		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
710		phy_type = "utmi";
711		clocks = <&tegra_car TEGRA114_CLK_USBD>,
712			 <&tegra_car TEGRA114_CLK_PLL_U>,
713			 <&tegra_car TEGRA114_CLK_USBD>;
714		clock-names = "reg", "pll_u", "utmi-pads";
715		resets = <&tegra_car 22>, <&tegra_car 22>;
716		reset-names = "usb", "utmi-pads";
717		#phy-cells = <0>;
718		nvidia,hssync-start-delay = <0>;
719		nvidia,idle-wait-delay = <17>;
720		nvidia,elastic-limit = <16>;
721		nvidia,term-range-adj = <6>;
722		nvidia,xcvr-setup = <9>;
723		nvidia,xcvr-lsfslew = <0>;
724		nvidia,xcvr-lsrslew = <3>;
725		nvidia,hssquelch-level = <2>;
726		nvidia,hsdiscon-level = <5>;
727		nvidia,xcvr-hsslew = <12>;
728		nvidia,has-utmi-pad-registers;
729		nvidia,pmc = <&tegra_pmc 0>;
730		status = "disabled";
731	};
732
733	usb@7d008000 {
734		compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci";
735		reg = <0x7d008000 0x4000>;
736		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
737		phy_type = "utmi";
738		clocks = <&tegra_car TEGRA114_CLK_USB3>;
739		resets = <&tegra_car 59>;
740		reset-names = "usb";
741		nvidia,phy = <&phy3>;
742		status = "disabled";
743	};
744
745	phy3: usb-phy@7d008000 {
746		compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
747		reg = <0x7d008000 0x4000>,
748		      <0x7d000000 0x4000>;
749		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
750		phy_type = "utmi";
751		clocks = <&tegra_car TEGRA114_CLK_USB3>,
752			 <&tegra_car TEGRA114_CLK_PLL_U>,
753			 <&tegra_car TEGRA114_CLK_USBD>;
754		clock-names = "reg", "pll_u", "utmi-pads";
755		resets = <&tegra_car 59>, <&tegra_car 22>;
756		reset-names = "usb", "utmi-pads";
757		#phy-cells = <0>;
758		nvidia,hssync-start-delay = <0>;
759		nvidia,idle-wait-delay = <17>;
760		nvidia,elastic-limit = <16>;
761		nvidia,term-range-adj = <6>;
762		nvidia,xcvr-setup = <9>;
763		nvidia,xcvr-lsfslew = <0>;
764		nvidia,xcvr-lsrslew = <3>;
765		nvidia,hssquelch-level = <2>;
766		nvidia,hsdiscon-level = <5>;
767		nvidia,xcvr-hsslew = <12>;
768		nvidia,pmc = <&tegra_pmc 2>;
769		status = "disabled";
770	};
771
772	cpus {
773		#address-cells = <1>;
774		#size-cells = <0>;
775
776		cpu@0 {
777			device_type = "cpu";
778			compatible = "arm,cortex-a15";
779			reg = <0>;
780		};
781
782		cpu@1 {
783			device_type = "cpu";
784			compatible = "arm,cortex-a15";
785			reg = <1>;
786		};
787
788		cpu@2 {
789			device_type = "cpu";
790			compatible = "arm,cortex-a15";
791			reg = <2>;
792		};
793
794		cpu@3 {
795			device_type = "cpu";
796			compatible = "arm,cortex-a15";
797			reg = <3>;
798		};
799	};
800
801	timer {
802		compatible = "arm,armv7-timer";
803		interrupts =
804			<GIC_PPI 13
805				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
806			<GIC_PPI 14
807				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
808			<GIC_PPI 11
809				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
810			<GIC_PPI 10
811				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
812		interrupt-parent = <&gic>;
813	};
814};
815