1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Author: Rory Bolt <rorybolt@pacbell.net> 4 * Copyright: (C) 2002 Rory Bolt 5 */ 6 7 #ifndef __IOP32X_IRQS_H 8 #define __IOP32X_IRQS_H 9 10 /* 11 * IOP80321 chipset interrupts 12 */ 13 #define IRQ_IOP32X_DMA0_EOT 0 14 #define IRQ_IOP32X_DMA0_EOC 1 15 #define IRQ_IOP32X_DMA1_EOT 2 16 #define IRQ_IOP32X_DMA1_EOC 3 17 #define IRQ_IOP32X_AA_EOT 6 18 #define IRQ_IOP32X_AA_EOC 7 19 #define IRQ_IOP32X_CORE_PMON 8 20 #define IRQ_IOP32X_TIMER0 9 21 #define IRQ_IOP32X_TIMER1 10 22 #define IRQ_IOP32X_I2C_0 11 23 #define IRQ_IOP32X_I2C_1 12 24 #define IRQ_IOP32X_MESSAGING 13 25 #define IRQ_IOP32X_ATU_BIST 14 26 #define IRQ_IOP32X_PERFMON 15 27 #define IRQ_IOP32X_CORE_PMU 16 28 #define IRQ_IOP32X_BIU_ERR 17 29 #define IRQ_IOP32X_ATU_ERR 18 30 #define IRQ_IOP32X_MCU_ERR 19 31 #define IRQ_IOP32X_DMA0_ERR 20 32 #define IRQ_IOP32X_DMA1_ERR 21 33 #define IRQ_IOP32X_AA_ERR 23 34 #define IRQ_IOP32X_MSG_ERR 24 35 #define IRQ_IOP32X_SSP 25 36 #define IRQ_IOP32X_XINT0 27 37 #define IRQ_IOP32X_XINT1 28 38 #define IRQ_IOP32X_XINT2 29 39 #define IRQ_IOP32X_XINT3 30 40 #define IRQ_IOP32X_HPI 31 41 42 #endif 43