1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ASM_MACH_IRQS_H 3 #define __ASM_MACH_IRQS_H 4 5 /* 6 * Interrupt numbers for PXA168 7 */ 8 #define IRQ_PXA168_NONE (-1) 9 #define IRQ_PXA168_SSP4 0 10 #define IRQ_PXA168_SSP3 1 11 #define IRQ_PXA168_SSP2 2 12 #define IRQ_PXA168_SSP1 3 13 #define IRQ_PXA168_PMIC_INT 4 14 #define IRQ_PXA168_RTC_INT 5 15 #define IRQ_PXA168_RTC_ALARM 6 16 #define IRQ_PXA168_TWSI0 7 17 #define IRQ_PXA168_GPU 8 18 #define IRQ_PXA168_KEYPAD 9 19 #define IRQ_PXA168_ONEWIRE 12 20 #define IRQ_PXA168_TIMER1 13 21 #define IRQ_PXA168_TIMER2 14 22 #define IRQ_PXA168_TIMER3 15 23 #define IRQ_PXA168_CMU 16 24 #define IRQ_PXA168_SSP5 17 25 #define IRQ_PXA168_MSP_WAKEUP 19 26 #define IRQ_PXA168_CF_WAKEUP 20 27 #define IRQ_PXA168_XD_WAKEUP 21 28 #define IRQ_PXA168_MFU 22 29 #define IRQ_PXA168_MSP 23 30 #define IRQ_PXA168_CF 24 31 #define IRQ_PXA168_XD 25 32 #define IRQ_PXA168_DDR_INT 26 33 #define IRQ_PXA168_UART1 27 34 #define IRQ_PXA168_UART2 28 35 #define IRQ_PXA168_UART3 29 36 #define IRQ_PXA168_WDT 35 37 #define IRQ_PXA168_MAIN_PMU 36 38 #define IRQ_PXA168_FRQ_CHANGE 38 39 #define IRQ_PXA168_SDH1 39 40 #define IRQ_PXA168_SDH2 40 41 #define IRQ_PXA168_LCD 41 42 #define IRQ_PXA168_CI 42 43 #define IRQ_PXA168_USB1 44 44 #define IRQ_PXA168_NAND 45 45 #define IRQ_PXA168_HIFI_DMA 46 46 #define IRQ_PXA168_DMA_INT0 47 47 #define IRQ_PXA168_DMA_INT1 48 48 #define IRQ_PXA168_GPIOX 49 49 #define IRQ_PXA168_USB2 51 50 #define IRQ_PXA168_AC97 57 51 #define IRQ_PXA168_TWSI1 58 52 #define IRQ_PXA168_AP_PMU 60 53 #define IRQ_PXA168_SM_INT 63 54 55 /* 56 * Interrupt numbers for PXA910 57 */ 58 #define IRQ_PXA910_NONE (-1) 59 #define IRQ_PXA910_AIRQ 0 60 #define IRQ_PXA910_SSP3 1 61 #define IRQ_PXA910_SSP2 2 62 #define IRQ_PXA910_SSP1 3 63 #define IRQ_PXA910_PMIC_INT 4 64 #define IRQ_PXA910_RTC_INT 5 65 #define IRQ_PXA910_RTC_ALARM 6 66 #define IRQ_PXA910_TWSI0 7 67 #define IRQ_PXA910_GPU 8 68 #define IRQ_PXA910_KEYPAD 9 69 #define IRQ_PXA910_ROTARY 10 70 #define IRQ_PXA910_TRACKBALL 11 71 #define IRQ_PXA910_ONEWIRE 12 72 #define IRQ_PXA910_AP1_TIMER1 13 73 #define IRQ_PXA910_AP1_TIMER2 14 74 #define IRQ_PXA910_AP1_TIMER3 15 75 #define IRQ_PXA910_IPC_AP0 16 76 #define IRQ_PXA910_IPC_AP1 17 77 #define IRQ_PXA910_IPC_AP2 18 78 #define IRQ_PXA910_IPC_AP3 19 79 #define IRQ_PXA910_IPC_AP4 20 80 #define IRQ_PXA910_IPC_CP0 21 81 #define IRQ_PXA910_IPC_CP1 22 82 #define IRQ_PXA910_IPC_CP2 23 83 #define IRQ_PXA910_IPC_CP3 24 84 #define IRQ_PXA910_IPC_CP4 25 85 #define IRQ_PXA910_L2_DDR 26 86 #define IRQ_PXA910_UART2 27 87 #define IRQ_PXA910_UART3 28 88 #define IRQ_PXA910_AP2_TIMER1 29 89 #define IRQ_PXA910_AP2_TIMER2 30 90 #define IRQ_PXA910_CP2_TIMER1 31 91 #define IRQ_PXA910_CP2_TIMER2 32 92 #define IRQ_PXA910_CP2_TIMER3 33 93 #define IRQ_PXA910_GSSP 34 94 #define IRQ_PXA910_CP2_WDT 35 95 #define IRQ_PXA910_MAIN_PMU 36 96 #define IRQ_PXA910_CP_FREQ_CHG 37 97 #define IRQ_PXA910_AP_FREQ_CHG 38 98 #define IRQ_PXA910_MMC 39 99 #define IRQ_PXA910_AEU 40 100 #define IRQ_PXA910_LCD 41 101 #define IRQ_PXA910_CCIC 42 102 #define IRQ_PXA910_IRE 43 103 #define IRQ_PXA910_USB1 44 104 #define IRQ_PXA910_NAND 45 105 #define IRQ_PXA910_HIFI_DMA 46 106 #define IRQ_PXA910_DMA_INT0 47 107 #define IRQ_PXA910_DMA_INT1 48 108 #define IRQ_PXA910_AP_GPIO 49 109 #define IRQ_PXA910_AP2_TIMER3 50 110 #define IRQ_PXA910_USB2 51 111 #define IRQ_PXA910_TWSI1 54 112 #define IRQ_PXA910_CP_GPIO 55 113 #define IRQ_PXA910_UART1 59 /* Slow UART */ 114 #define IRQ_PXA910_AP_PMU 60 115 #define IRQ_PXA910_SM_INT 63 /* from PinMux */ 116 117 /* 118 * Interrupt numbers for MMP2 119 */ 120 #define IRQ_MMP2_NONE (-1) 121 #define IRQ_MMP2_SSP1 0 122 #define IRQ_MMP2_SSP2 1 123 #define IRQ_MMP2_SSPA1 2 124 #define IRQ_MMP2_SSPA2 3 125 #define IRQ_MMP2_PMIC_MUX 4 /* PMIC & Charger */ 126 #define IRQ_MMP2_RTC_MUX 5 127 #define IRQ_MMP2_TWSI1 7 128 #define IRQ_MMP2_GPU 8 129 #define IRQ_MMP2_KEYPAD_MUX 9 130 #define IRQ_MMP2_ROTARY 10 131 #define IRQ_MMP2_TRACKBALL 11 132 #define IRQ_MMP2_ONEWIRE 12 133 #define IRQ_MMP2_TIMER1 13 134 #define IRQ_MMP2_TIMER2 14 135 #define IRQ_MMP2_TIMER3 15 136 #define IRQ_MMP2_RIPC 16 137 #define IRQ_MMP2_TWSI_MUX 17 /* TWSI2 ~ TWSI6 */ 138 #define IRQ_MMP2_HDMI 19 139 #define IRQ_MMP2_SSP3 20 140 #define IRQ_MMP2_SSP4 21 141 #define IRQ_MMP2_USB_HS1 22 142 #define IRQ_MMP2_USB_HS2 23 143 #define IRQ_MMP2_UART3 24 144 #define IRQ_MMP2_UART1 27 145 #define IRQ_MMP2_UART2 28 146 #define IRQ_MMP2_MIPI_DSI 29 147 #define IRQ_MMP2_CI2 30 148 #define IRQ_MMP2_PMU_TIMER1 31 149 #define IRQ_MMP2_PMU_TIMER2 32 150 #define IRQ_MMP2_PMU_TIMER3 33 151 #define IRQ_MMP2_USB_FS 34 152 #define IRQ_MMP2_MISC_MUX 35 153 #define IRQ_MMP2_WDT1 36 154 #define IRQ_MMP2_NAND_DMA 37 155 #define IRQ_MMP2_USIM 38 156 #define IRQ_MMP2_MMC 39 157 #define IRQ_MMP2_WTM 40 158 #define IRQ_MMP2_LCD 41 159 #define IRQ_MMP2_CI 42 160 #define IRQ_MMP2_IRE 43 161 #define IRQ_MMP2_USB_OTG 44 162 #define IRQ_MMP2_NAND 45 163 #define IRQ_MMP2_UART4 46 164 #define IRQ_MMP2_DMA_FIQ 47 165 #define IRQ_MMP2_DMA_RIQ 48 166 #define IRQ_MMP2_GPIO 49 167 #define IRQ_MMP2_MIPI_HSI1_MUX 51 168 #define IRQ_MMP2_MMC2 52 169 #define IRQ_MMP2_MMC3 53 170 #define IRQ_MMP2_MMC4 54 171 #define IRQ_MMP2_MIPI_HSI0_MUX 55 172 #define IRQ_MMP2_MSP 58 173 #define IRQ_MMP2_MIPI_SLIM_DMA 59 174 #define IRQ_MMP2_PJ4_FREQ_CHG 60 175 #define IRQ_MMP2_MIPI_SLIM 62 176 #define IRQ_MMP2_SM 63 177 178 #define IRQ_MMP2_MUX_BASE 64 179 180 /* secondary interrupt of INT #4 */ 181 #define IRQ_MMP2_PMIC_BASE (IRQ_MMP2_MUX_BASE) 182 #define IRQ_MMP2_CHARGER (IRQ_MMP2_PMIC_BASE + 0) 183 #define IRQ_MMP2_PMIC (IRQ_MMP2_PMIC_BASE + 1) 184 185 /* secondary interrupt of INT #5 */ 186 #define IRQ_MMP2_RTC_BASE (IRQ_MMP2_PMIC_BASE + 2) 187 #define IRQ_MMP2_RTC_ALARM (IRQ_MMP2_RTC_BASE + 0) 188 #define IRQ_MMP2_RTC (IRQ_MMP2_RTC_BASE + 1) 189 190 /* secondary interrupt of INT #9 */ 191 #define IRQ_MMP2_KEYPAD_BASE (IRQ_MMP2_RTC_BASE + 2) 192 #define IRQ_MMP2_KPC (IRQ_MMP2_KEYPAD_BASE + 0) 193 #define IRQ_MMP2_ROTORY (IRQ_MMP2_KEYPAD_BASE + 1) 194 #define IRQ_MMP2_TBALL (IRQ_MMP2_KEYPAD_BASE + 2) 195 196 /* secondary interrupt of INT #17 */ 197 #define IRQ_MMP2_TWSI_BASE (IRQ_MMP2_KEYPAD_BASE + 3) 198 #define IRQ_MMP2_TWSI2 (IRQ_MMP2_TWSI_BASE + 0) 199 #define IRQ_MMP2_TWSI3 (IRQ_MMP2_TWSI_BASE + 1) 200 #define IRQ_MMP2_TWSI4 (IRQ_MMP2_TWSI_BASE + 2) 201 #define IRQ_MMP2_TWSI5 (IRQ_MMP2_TWSI_BASE + 3) 202 #define IRQ_MMP2_TWSI6 (IRQ_MMP2_TWSI_BASE + 4) 203 204 /* secondary interrupt of INT #35 */ 205 #define IRQ_MMP2_MISC_BASE (IRQ_MMP2_TWSI_BASE + 5) 206 #define IRQ_MMP2_PERF (IRQ_MMP2_MISC_BASE + 0) 207 #define IRQ_MMP2_L2_PA_ECC (IRQ_MMP2_MISC_BASE + 1) 208 #define IRQ_MMP2_L2_ECC (IRQ_MMP2_MISC_BASE + 2) 209 #define IRQ_MMP2_L2_UECC (IRQ_MMP2_MISC_BASE + 3) 210 #define IRQ_MMP2_DDR (IRQ_MMP2_MISC_BASE + 4) 211 #define IRQ_MMP2_FAB0_TIMEOUT (IRQ_MMP2_MISC_BASE + 5) 212 #define IRQ_MMP2_FAB1_TIMEOUT (IRQ_MMP2_MISC_BASE + 6) 213 #define IRQ_MMP2_FAB2_TIMEOUT (IRQ_MMP2_MISC_BASE + 7) 214 #define IRQ_MMP2_THERMAL (IRQ_MMP2_MISC_BASE + 9) 215 #define IRQ_MMP2_MAIN_PMU (IRQ_MMP2_MISC_BASE + 10) 216 #define IRQ_MMP2_WDT2 (IRQ_MMP2_MISC_BASE + 11) 217 #define IRQ_MMP2_CORESIGHT (IRQ_MMP2_MISC_BASE + 12) 218 #define IRQ_MMP2_COMMTX (IRQ_MMP2_MISC_BASE + 13) 219 #define IRQ_MMP2_COMMRX (IRQ_MMP2_MISC_BASE + 14) 220 221 /* secondary interrupt of INT #51 */ 222 #define IRQ_MMP2_MIPI_HSI1_BASE (IRQ_MMP2_MISC_BASE + 15) 223 #define IRQ_MMP2_HSI1_CAWAKE (IRQ_MMP2_MIPI_HSI1_BASE + 0) 224 #define IRQ_MMP2_MIPI_HSI_INT1 (IRQ_MMP2_MIPI_HSI1_BASE + 1) 225 226 /* secondary interrupt of INT #55 */ 227 #define IRQ_MMP2_MIPI_HSI0_BASE (IRQ_MMP2_MIPI_HSI1_BASE + 2) 228 #define IRQ_MMP2_HSI0_CAWAKE (IRQ_MMP2_MIPI_HSI0_BASE + 0) 229 #define IRQ_MMP2_MIPI_HSI_INT0 (IRQ_MMP2_MIPI_HSI0_BASE + 1) 230 231 #define IRQ_MMP2_MUX_END (IRQ_MMP2_MIPI_HSI0_BASE + 2) 232 233 #define IRQ_GPIO_START 128 234 #define MMP_NR_BUILTIN_GPIO 192 235 #define MMP_GPIO_TO_IRQ(gpio) (IRQ_GPIO_START + (gpio)) 236 237 #define IRQ_BOARD_START (IRQ_GPIO_START + MMP_NR_BUILTIN_GPIO) 238 #define MMP_NR_IRQS IRQ_BOARD_START 239 240 #endif /* __ASM_MACH_IRQS_H */ 241