1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /************************************************************************ 3 * Include file for TRIZEPS4 SoM and ConXS eval-board 4 * Copyright (c) Jürgen Schindele 5 * 2006 6 ************************************************************************/ 7 8 /* 9 * Includes/Defines 10 */ 11 #ifndef _TRIPEPS4_H_ 12 #define _TRIPEPS4_H_ 13 14 #include "irqs.h" /* PXA_GPIO_TO_IRQ */ 15 16 /* physical memory regions */ 17 #define TRIZEPS4_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */ 18 #define TRIZEPS4_DISK_PHYS (PXA_CS1_PHYS) /* Disk On Chip region */ 19 #define TRIZEPS4_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */ 20 #define TRIZEPS4_PIC_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board */ 21 #define TRIZEPS4_SDRAM_BASE 0xa0000000 /* SDRAM region */ 22 23 /* Logic on ConXS-board CSFR register*/ 24 #define TRIZEPS4_CFSR_PHYS (PXA_CS3_PHYS) 25 /* Logic on ConXS-board BOCR register*/ 26 #define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000) 27 /* Logic on ConXS-board IRCR register*/ 28 #define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000) 29 /* Logic on ConXS-board UPSR register*/ 30 #define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000) 31 /* Logic on ConXS-board DICR register*/ 32 #define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000) 33 34 /* virtual memory regions */ 35 #define TRIZEPS4_DISK_VIRT 0xF0000000 /* Disk On Chip region */ 36 37 #define TRIZEPS4_PIC_VIRT 0xF0100000 /* not used */ 38 #define TRIZEPS4_CFSR_VIRT 0xF0100000 39 #define TRIZEPS4_BOCR_VIRT 0xF0200000 40 #define TRIZEPS4_DICR_VIRT 0xF0300000 41 #define TRIZEPS4_IRCR_VIRT 0xF0400000 42 #define TRIZEPS4_UPSR_VIRT 0xF0500000 43 44 /* size of flash */ 45 #define TRIZEPS4_FLASH_SIZE 0x02000000 /* Flash size 32 MB */ 46 47 /* Ethernet Controller Davicom DM9000 */ 48 #define GPIO_DM9000 101 49 #define TRIZEPS4_ETH_IRQ PXA_GPIO_TO_IRQ(GPIO_DM9000) 50 51 /* UCB1400 audio / TS-controller */ 52 #define GPIO_UCB1400 1 53 #define TRIZEPS4_UCB1400_IRQ PXA_GPIO_TO_IRQ(GPIO_UCB1400) 54 55 /* PCMCIA socket Compact Flash */ 56 #define GPIO_PCD 11 /* PCMCIA Card Detect */ 57 #define TRIZEPS4_CD_IRQ PXA_GPIO_TO_IRQ(GPIO_PCD) 58 #define GPIO_PRDY 13 /* READY / nINT */ 59 #define TRIZEPS4_READY_NINT PXA_GPIO_TO_IRQ(GPIO_PRDY) 60 61 /* MMC socket */ 62 #define GPIO_MMC_DET 12 63 #define TRIZEPS4_MMC_IRQ PXA_GPIO_TO_IRQ(GPIO_MMC_DET) 64 65 /* DOC NAND chip */ 66 #define GPIO_DOC_LOCK 94 67 #define GPIO_DOC_IRQ 93 68 #define TRIZEPS4_DOC_IRQ PXA_GPIO_TO_IRQ(GPIO_DOC_IRQ) 69 70 /* SPI interface */ 71 #define GPIO_SPI 53 72 #define TRIZEPS4_SPI_IRQ PXA_GPIO_TO_IRQ(GPIO_SPI) 73 74 /* LEDS using tx2 / rx2 */ 75 #define GPIO_SYS_BUSY_LED 46 76 #define GPIO_HEARTBEAT_LED 47 77 78 /* Off-module PIC on ConXS board */ 79 #define GPIO_PIC 0 80 #define TRIZEPS4_PIC_IRQ PXA_GPIO_TO_IRQ(GPIO_PIC) 81 82 #ifdef CONFIG_MACH_TRIZEPS_CONXS 83 /* for CONXS base board define these registers */ 84 #define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT) 85 #define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS) 86 87 #define BCR_P2V(x) ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT) 88 #define BCR_V2P(x) ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS) 89 90 #define DCR_P2V(x) ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT) 91 #define DCR_V2P(x) ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS) 92 93 #define IRCR_P2V(x) ((x) - TRIZEPS4_IRCR_PHYS + TRIZEPS4_IRCR_VIRT) 94 #define IRCR_V2P(x) ((x) - TRIZEPS4_IRCR_VIRT + TRIZEPS4_IRCR_PHYS) 95 96 #ifndef __ASSEMBLY__ CFSR_readw(void)97static inline unsigned short CFSR_readw(void) 98 { 99 /* [Compact Flash Status Register] is read only */ 100 return *((unsigned short *)CFSR_P2V(0x0C000000)); 101 } BCR_writew(unsigned short value)102static inline void BCR_writew(unsigned short value) 103 { 104 /* [Board Control Regsiter] is write only */ 105 *((unsigned short *)BCR_P2V(0x0E000000)) = value; 106 } DCR_writew(unsigned short value)107static inline void DCR_writew(unsigned short value) 108 { 109 /* [Display Control Register] is write only */ 110 *((unsigned short *)DCR_P2V(0x0E000000)) = value; 111 } IRCR_writew(unsigned short value)112static inline void IRCR_writew(unsigned short value) 113 { 114 /* [InfraRed data Control Register] is write only */ 115 *((unsigned short *)IRCR_P2V(0x0E000000)) = value; 116 } 117 #else 118 #define ConXS_CFSR CFSR_P2V(0x0C000000) 119 #define ConXS_BCR BCR_P2V(0x0E000000) 120 #define ConXS_DCR DCR_P2V(0x0F800000) 121 #define ConXS_IRCR IRCR_P2V(0x0F800000) 122 #endif 123 #else 124 /* for whatever baseboard define function registers */ CFSR_readw(void)125static inline unsigned short CFSR_readw(void) 126 { 127 return 0; 128 } BCR_writew(unsigned short value)129static inline void BCR_writew(unsigned short value) 130 { 131 ; 132 } DCR_writew(unsigned short value)133static inline void DCR_writew(unsigned short value) 134 { 135 ; 136 } IRCR_writew(unsigned short value)137static inline void IRCR_writew(unsigned short value) 138 { 139 ; 140 } 141 #endif /* CONFIG_MACH_TRIZEPS_CONXS */ 142 143 #define ConXS_CFSR_BVD_MASK 0x0003 144 #define ConXS_CFSR_BVD1 (1 << 0) 145 #define ConXS_CFSR_BVD2 (1 << 1) 146 #define ConXS_CFSR_VS_MASK 0x000C 147 #define ConXS_CFSR_VS1 (1 << 2) 148 #define ConXS_CFSR_VS2 (1 << 3) 149 #define ConXS_CFSR_VS_5V (0x3 << 2) 150 #define ConXS_CFSR_VS_3V3 0x0 151 152 #define ConXS_BCR_S0_POW_EN0 (1 << 0) 153 #define ConXS_BCR_S0_POW_EN1 (1 << 1) 154 #define ConXS_BCR_L_DISP (1 << 4) 155 #define ConXS_BCR_CF_BUF_EN (1 << 5) 156 #define ConXS_BCR_CF_RESET (1 << 7) 157 #define ConXS_BCR_S0_VCC_3V3 0x1 158 #define ConXS_BCR_S0_VCC_5V0 0x2 159 #define ConXS_BCR_S0_VPP_12V 0x4 160 #define ConXS_BCR_S0_VPP_3V3 0x8 161 162 #define ConXS_IRCR_MODE (1 << 0) 163 #define ConXS_IRCR_SD (1 << 1) 164 165 #endif /* _TRIPEPS4_H_ */ 166