1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2005 Simtec Electronics 4 * http://www.simtec.co.uk/products/ 5 * Ben Dooks <ben@simtec.co.uk> 6 * 7 * ANUBIS - CPLD control constants 8 * ANUBIS - IRQ Number definitions 9 * ANUBIS - Memory map definitions 10 */ 11 12 #ifndef __MACH_S3C24XX_ANUBIS_H 13 #define __MACH_S3C24XX_ANUBIS_H __FILE__ 14 15 /* CTRL2 - NAND WP control, IDE Reset assert/check */ 16 17 #define ANUBIS_CTRL1_NANDSEL (0x3) 18 19 /* IDREG - revision */ 20 21 #define ANUBIS_IDREG_REVMASK (0x7) 22 23 /* irq */ 24 25 #define ANUBIS_IRQ_IDE0 IRQ_EINT2 26 #define ANUBIS_IRQ_IDE1 IRQ_EINT3 27 #define ANUBIS_IRQ_ASIX IRQ_EINT1 28 29 /* map */ 30 31 /* start peripherals off after the S3C2410 */ 32 33 #define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000)) 34 35 #define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26)) 36 37 /* we put the CPLD registers next, to get them out of the way */ 38 39 #define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) 40 #define ANUBIS_PA_CTRL1 ANUBIS_PA_CPLD 41 42 #define ANUBIS_VA_IDREG ANUBIS_IOADDR(0x00300000) 43 #define ANUBIS_PA_IDREG (ANUBIS_PA_CPLD + (3 << 23)) 44 45 #define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000) 46 #define ANUBIS_IDEPRIAUX ANUBIS_IOADDR(0x01100000) 47 #define ANUBIS_IDESEC ANUBIS_IOADDR(0x01200000) 48 #define ANUBIS_IDESECAUX ANUBIS_IOADDR(0x01300000) 49 50 #endif /* __MACH_S3C24XX_ANUBIS_H */ 51