1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/clock/mt8173-clk.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/memory/mt8173-larb-port.h> 18#include <dt-bindings/phy/phy.h> 19#include <dt-bindings/power/mt8173-power.h> 20#include <dt-bindings/reset/mt8173-resets.h> 21#include <dt-bindings/gce/mt8173-gce.h> 22#include <dt-bindings/thermal/thermal.h> 23#include "mt8173-pinfunc.h" 24 25/ { 26 compatible = "mediatek,mt8173"; 27 interrupt-parent = <&sysirq>; 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 aliases { 32 ovl0 = &ovl0; 33 ovl1 = &ovl1; 34 rdma0 = &rdma0; 35 rdma1 = &rdma1; 36 rdma2 = &rdma2; 37 wdma0 = &wdma0; 38 wdma1 = &wdma1; 39 color0 = &color0; 40 color1 = &color1; 41 split0 = &split0; 42 split1 = &split1; 43 dpi0 = &dpi0; 44 dsi0 = &dsi0; 45 dsi1 = &dsi1; 46 mdp-rdma0 = &mdp_rdma0; 47 mdp-rdma1 = &mdp_rdma1; 48 mdp-rsz0 = &mdp_rsz0; 49 mdp-rsz1 = &mdp_rsz1; 50 mdp-rsz2 = &mdp_rsz2; 51 mdp-wdma0 = &mdp_wdma0; 52 mdp-wrot0 = &mdp_wrot0; 53 mdp-wrot1 = &mdp_wrot1; 54 serial0 = &uart0; 55 serial1 = &uart1; 56 serial2 = &uart2; 57 serial3 = &uart3; 58 }; 59 60 cluster0_opp: opp_table0 { 61 compatible = "operating-points-v2"; 62 opp-shared; 63 opp-507000000 { 64 opp-hz = /bits/ 64 <507000000>; 65 opp-microvolt = <859000>; 66 }; 67 opp-702000000 { 68 opp-hz = /bits/ 64 <702000000>; 69 opp-microvolt = <908000>; 70 }; 71 opp-1001000000 { 72 opp-hz = /bits/ 64 <1001000000>; 73 opp-microvolt = <983000>; 74 }; 75 opp-1105000000 { 76 opp-hz = /bits/ 64 <1105000000>; 77 opp-microvolt = <1009000>; 78 }; 79 opp-1209000000 { 80 opp-hz = /bits/ 64 <1209000000>; 81 opp-microvolt = <1034000>; 82 }; 83 opp-1300000000 { 84 opp-hz = /bits/ 64 <1300000000>; 85 opp-microvolt = <1057000>; 86 }; 87 opp-1508000000 { 88 opp-hz = /bits/ 64 <1508000000>; 89 opp-microvolt = <1109000>; 90 }; 91 opp-1703000000 { 92 opp-hz = /bits/ 64 <1703000000>; 93 opp-microvolt = <1125000>; 94 }; 95 }; 96 97 cluster1_opp: opp_table1 { 98 compatible = "operating-points-v2"; 99 opp-shared; 100 opp-507000000 { 101 opp-hz = /bits/ 64 <507000000>; 102 opp-microvolt = <828000>; 103 }; 104 opp-702000000 { 105 opp-hz = /bits/ 64 <702000000>; 106 opp-microvolt = <867000>; 107 }; 108 opp-1001000000 { 109 opp-hz = /bits/ 64 <1001000000>; 110 opp-microvolt = <927000>; 111 }; 112 opp-1209000000 { 113 opp-hz = /bits/ 64 <1209000000>; 114 opp-microvolt = <968000>; 115 }; 116 opp-1404000000 { 117 opp-hz = /bits/ 64 <1404000000>; 118 opp-microvolt = <1007000>; 119 }; 120 opp-1612000000 { 121 opp-hz = /bits/ 64 <1612000000>; 122 opp-microvolt = <1049000>; 123 }; 124 opp-1807000000 { 125 opp-hz = /bits/ 64 <1807000000>; 126 opp-microvolt = <1089000>; 127 }; 128 opp-2106000000 { 129 opp-hz = /bits/ 64 <2106000000>; 130 opp-microvolt = <1125000>; 131 }; 132 }; 133 134 cpus { 135 #address-cells = <1>; 136 #size-cells = <0>; 137 138 cpu-map { 139 cluster0 { 140 core0 { 141 cpu = <&cpu0>; 142 }; 143 core1 { 144 cpu = <&cpu1>; 145 }; 146 }; 147 148 cluster1 { 149 core0 { 150 cpu = <&cpu2>; 151 }; 152 core1 { 153 cpu = <&cpu3>; 154 }; 155 }; 156 }; 157 158 cpu0: cpu@0 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a53"; 161 reg = <0x000>; 162 enable-method = "psci"; 163 cpu-idle-states = <&CPU_SLEEP_0>; 164 #cooling-cells = <2>; 165 dynamic-power-coefficient = <263>; 166 clocks = <&infracfg CLK_INFRA_CA53SEL>, 167 <&apmixedsys CLK_APMIXED_MAINPLL>; 168 clock-names = "cpu", "intermediate"; 169 operating-points-v2 = <&cluster0_opp>; 170 capacity-dmips-mhz = <740>; 171 }; 172 173 cpu1: cpu@1 { 174 device_type = "cpu"; 175 compatible = "arm,cortex-a53"; 176 reg = <0x001>; 177 enable-method = "psci"; 178 cpu-idle-states = <&CPU_SLEEP_0>; 179 #cooling-cells = <2>; 180 dynamic-power-coefficient = <263>; 181 clocks = <&infracfg CLK_INFRA_CA53SEL>, 182 <&apmixedsys CLK_APMIXED_MAINPLL>; 183 clock-names = "cpu", "intermediate"; 184 operating-points-v2 = <&cluster0_opp>; 185 capacity-dmips-mhz = <740>; 186 }; 187 188 cpu2: cpu@100 { 189 device_type = "cpu"; 190 compatible = "arm,cortex-a72"; 191 reg = <0x100>; 192 enable-method = "psci"; 193 cpu-idle-states = <&CPU_SLEEP_0>; 194 #cooling-cells = <2>; 195 dynamic-power-coefficient = <530>; 196 clocks = <&infracfg CLK_INFRA_CA72SEL>, 197 <&apmixedsys CLK_APMIXED_MAINPLL>; 198 clock-names = "cpu", "intermediate"; 199 operating-points-v2 = <&cluster1_opp>; 200 capacity-dmips-mhz = <1024>; 201 }; 202 203 cpu3: cpu@101 { 204 device_type = "cpu"; 205 compatible = "arm,cortex-a72"; 206 reg = <0x101>; 207 enable-method = "psci"; 208 cpu-idle-states = <&CPU_SLEEP_0>; 209 #cooling-cells = <2>; 210 dynamic-power-coefficient = <530>; 211 clocks = <&infracfg CLK_INFRA_CA72SEL>, 212 <&apmixedsys CLK_APMIXED_MAINPLL>; 213 clock-names = "cpu", "intermediate"; 214 operating-points-v2 = <&cluster1_opp>; 215 capacity-dmips-mhz = <1024>; 216 }; 217 218 idle-states { 219 entry-method = "psci"; 220 221 CPU_SLEEP_0: cpu-sleep-0 { 222 compatible = "arm,idle-state"; 223 local-timer-stop; 224 entry-latency-us = <639>; 225 exit-latency-us = <680>; 226 min-residency-us = <1088>; 227 arm,psci-suspend-param = <0x0010000>; 228 }; 229 }; 230 }; 231 232 pmu_a53 { 233 compatible = "arm,cortex-a53-pmu"; 234 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 235 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>; 236 interrupt-affinity = <&cpu0>, <&cpu1>; 237 }; 238 239 pmu_a72 { 240 compatible = "arm,cortex-a72-pmu"; 241 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>, 242 <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>; 243 interrupt-affinity = <&cpu2>, <&cpu3>; 244 }; 245 246 psci { 247 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 248 method = "smc"; 249 cpu_suspend = <0x84000001>; 250 cpu_off = <0x84000002>; 251 cpu_on = <0x84000003>; 252 }; 253 254 clk26m: oscillator0 { 255 compatible = "fixed-clock"; 256 #clock-cells = <0>; 257 clock-frequency = <26000000>; 258 clock-output-names = "clk26m"; 259 }; 260 261 clk32k: oscillator1 { 262 compatible = "fixed-clock"; 263 #clock-cells = <0>; 264 clock-frequency = <32000>; 265 clock-output-names = "clk32k"; 266 }; 267 268 cpum_ck: oscillator2 { 269 compatible = "fixed-clock"; 270 #clock-cells = <0>; 271 clock-frequency = <0>; 272 clock-output-names = "cpum_ck"; 273 }; 274 275 thermal-zones { 276 cpu_thermal: cpu_thermal { 277 polling-delay-passive = <1000>; /* milliseconds */ 278 polling-delay = <1000>; /* milliseconds */ 279 280 thermal-sensors = <&thermal>; 281 sustainable-power = <1500>; /* milliwatts */ 282 283 trips { 284 threshold: trip-point0 { 285 temperature = <68000>; 286 hysteresis = <2000>; 287 type = "passive"; 288 }; 289 290 target: trip-point1 { 291 temperature = <85000>; 292 hysteresis = <2000>; 293 type = "passive"; 294 }; 295 296 cpu_crit: cpu_crit0 { 297 temperature = <115000>; 298 hysteresis = <2000>; 299 type = "critical"; 300 }; 301 }; 302 303 cooling-maps { 304 map0 { 305 trip = <&target>; 306 cooling-device = <&cpu0 THERMAL_NO_LIMIT 307 THERMAL_NO_LIMIT>, 308 <&cpu1 THERMAL_NO_LIMIT 309 THERMAL_NO_LIMIT>; 310 contribution = <3072>; 311 }; 312 map1 { 313 trip = <&target>; 314 cooling-device = <&cpu2 THERMAL_NO_LIMIT 315 THERMAL_NO_LIMIT>, 316 <&cpu3 THERMAL_NO_LIMIT 317 THERMAL_NO_LIMIT>; 318 contribution = <1024>; 319 }; 320 }; 321 }; 322 }; 323 324 reserved-memory { 325 #address-cells = <2>; 326 #size-cells = <2>; 327 ranges; 328 vpu_dma_reserved: vpu_dma_mem_region@b7000000 { 329 compatible = "shared-dma-pool"; 330 reg = <0 0xb7000000 0 0x500000>; 331 alignment = <0x1000>; 332 no-map; 333 }; 334 }; 335 336 timer { 337 compatible = "arm,armv8-timer"; 338 interrupt-parent = <&gic>; 339 interrupts = <GIC_PPI 13 340 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 341 <GIC_PPI 14 342 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 343 <GIC_PPI 11 344 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 345 <GIC_PPI 10 346 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 347 arm,no-tick-in-suspend; 348 }; 349 350 soc { 351 #address-cells = <2>; 352 #size-cells = <2>; 353 compatible = "simple-bus"; 354 ranges; 355 356 topckgen: clock-controller@10000000 { 357 compatible = "mediatek,mt8173-topckgen"; 358 reg = <0 0x10000000 0 0x1000>; 359 #clock-cells = <1>; 360 }; 361 362 infracfg: power-controller@10001000 { 363 compatible = "mediatek,mt8173-infracfg", "syscon"; 364 reg = <0 0x10001000 0 0x1000>; 365 #clock-cells = <1>; 366 #reset-cells = <1>; 367 }; 368 369 pericfg: power-controller@10003000 { 370 compatible = "mediatek,mt8173-pericfg", "syscon"; 371 reg = <0 0x10003000 0 0x1000>; 372 #clock-cells = <1>; 373 #reset-cells = <1>; 374 }; 375 376 syscfg_pctl_a: syscfg_pctl_a@10005000 { 377 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 378 reg = <0 0x10005000 0 0x1000>; 379 }; 380 381 pio: pinctrl@1000b000 { 382 compatible = "mediatek,mt8173-pinctrl"; 383 reg = <0 0x1000b000 0 0x1000>; 384 mediatek,pctl-regmap = <&syscfg_pctl_a>; 385 pins-are-numbered; 386 gpio-controller; 387 #gpio-cells = <2>; 388 interrupt-controller; 389 #interrupt-cells = <2>; 390 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 393 394 hdmi_pin: xxx { 395 396 /*hdmi htplg pin*/ 397 pins1 { 398 pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 399 input-enable; 400 bias-pull-down; 401 }; 402 }; 403 404 i2c0_pins_a: i2c0 { 405 pins1 { 406 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 407 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 408 bias-disable; 409 }; 410 }; 411 412 i2c1_pins_a: i2c1 { 413 pins1 { 414 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 415 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 416 bias-disable; 417 }; 418 }; 419 420 i2c2_pins_a: i2c2 { 421 pins1 { 422 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 423 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 424 bias-disable; 425 }; 426 }; 427 428 i2c3_pins_a: i2c3 { 429 pins1 { 430 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 431 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 432 bias-disable; 433 }; 434 }; 435 436 i2c4_pins_a: i2c4 { 437 pins1 { 438 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 439 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 440 bias-disable; 441 }; 442 }; 443 444 i2c6_pins_a: i2c6 { 445 pins1 { 446 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 447 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 448 bias-disable; 449 }; 450 }; 451 }; 452 453 scpsys: syscon@10006000 { 454 compatible = "syscon", "simple-mfd"; 455 reg = <0 0x10006000 0 0x1000>; 456 #power-domain-cells = <1>; 457 458 /* System Power Manager */ 459 spm: power-controller { 460 compatible = "mediatek,mt8173-power-controller"; 461 #address-cells = <1>; 462 #size-cells = <0>; 463 #power-domain-cells = <1>; 464 465 /* power domains of the SoC */ 466 power-domain@MT8173_POWER_DOMAIN_VDEC { 467 reg = <MT8173_POWER_DOMAIN_VDEC>; 468 clocks = <&topckgen CLK_TOP_MM_SEL>; 469 clock-names = "mm"; 470 #power-domain-cells = <0>; 471 }; 472 power-domain@MT8173_POWER_DOMAIN_VENC { 473 reg = <MT8173_POWER_DOMAIN_VENC>; 474 clocks = <&topckgen CLK_TOP_MM_SEL>, 475 <&topckgen CLK_TOP_VENC_SEL>; 476 clock-names = "mm", "venc"; 477 #power-domain-cells = <0>; 478 }; 479 power-domain@MT8173_POWER_DOMAIN_ISP { 480 reg = <MT8173_POWER_DOMAIN_ISP>; 481 clocks = <&topckgen CLK_TOP_MM_SEL>; 482 clock-names = "mm"; 483 #power-domain-cells = <0>; 484 }; 485 power-domain@MT8173_POWER_DOMAIN_MM { 486 reg = <MT8173_POWER_DOMAIN_MM>; 487 clocks = <&topckgen CLK_TOP_MM_SEL>; 488 clock-names = "mm"; 489 #power-domain-cells = <0>; 490 mediatek,infracfg = <&infracfg>; 491 }; 492 power-domain@MT8173_POWER_DOMAIN_VENC_LT { 493 reg = <MT8173_POWER_DOMAIN_VENC_LT>; 494 clocks = <&topckgen CLK_TOP_MM_SEL>, 495 <&topckgen CLK_TOP_VENC_LT_SEL>; 496 clock-names = "mm", "venclt"; 497 #power-domain-cells = <0>; 498 }; 499 power-domain@MT8173_POWER_DOMAIN_AUDIO { 500 reg = <MT8173_POWER_DOMAIN_AUDIO>; 501 #power-domain-cells = <0>; 502 }; 503 power-domain@MT8173_POWER_DOMAIN_USB { 504 reg = <MT8173_POWER_DOMAIN_USB>; 505 #power-domain-cells = <0>; 506 }; 507 mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC { 508 reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>; 509 clocks = <&clk26m>; 510 clock-names = "mfg"; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 #power-domain-cells = <1>; 514 515 power-domain@MT8173_POWER_DOMAIN_MFG_2D { 516 reg = <MT8173_POWER_DOMAIN_MFG_2D>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 #power-domain-cells = <1>; 520 521 power-domain@MT8173_POWER_DOMAIN_MFG { 522 reg = <MT8173_POWER_DOMAIN_MFG>; 523 #power-domain-cells = <0>; 524 mediatek,infracfg = <&infracfg>; 525 }; 526 }; 527 }; 528 }; 529 }; 530 531 watchdog: watchdog@10007000 { 532 compatible = "mediatek,mt8173-wdt", 533 "mediatek,mt6589-wdt"; 534 reg = <0 0x10007000 0 0x100>; 535 }; 536 537 pwrap: pwrap@1000d000 { 538 compatible = "mediatek,mt8173-pwrap"; 539 reg = <0 0x1000d000 0 0x1000>; 540 reg-names = "pwrap"; 541 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 542 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 543 reset-names = "pwrap"; 544 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 545 clock-names = "spi", "wrap"; 546 }; 547 548 cec: cec@10013000 { 549 compatible = "mediatek,mt8173-cec"; 550 reg = <0 0x10013000 0 0xbc>; 551 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 552 clocks = <&infracfg CLK_INFRA_CEC>; 553 status = "disabled"; 554 }; 555 556 vpu: vpu@10020000 { 557 compatible = "mediatek,mt8173-vpu"; 558 reg = <0 0x10020000 0 0x30000>, 559 <0 0x10050000 0 0x100>; 560 reg-names = "tcm", "cfg_reg"; 561 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&topckgen CLK_TOP_SCP_SEL>; 563 clock-names = "main"; 564 memory-region = <&vpu_dma_reserved>; 565 }; 566 567 sysirq: intpol-controller@10200620 { 568 compatible = "mediatek,mt8173-sysirq", 569 "mediatek,mt6577-sysirq"; 570 interrupt-controller; 571 #interrupt-cells = <3>; 572 interrupt-parent = <&gic>; 573 reg = <0 0x10200620 0 0x20>; 574 }; 575 576 iommu: iommu@10205000 { 577 compatible = "mediatek,mt8173-m4u"; 578 reg = <0 0x10205000 0 0x1000>; 579 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 580 clocks = <&infracfg CLK_INFRA_M4U>; 581 clock-names = "bclk"; 582 mediatek,larbs = <&larb0 &larb1 &larb2 583 &larb3 &larb4 &larb5>; 584 #iommu-cells = <1>; 585 }; 586 587 efuse: efuse@10206000 { 588 compatible = "mediatek,mt8173-efuse"; 589 reg = <0 0x10206000 0 0x1000>; 590 #address-cells = <1>; 591 #size-cells = <1>; 592 thermal_calibration: calib@528 { 593 reg = <0x528 0xc>; 594 }; 595 }; 596 597 apmixedsys: clock-controller@10209000 { 598 compatible = "mediatek,mt8173-apmixedsys"; 599 reg = <0 0x10209000 0 0x1000>; 600 #clock-cells = <1>; 601 }; 602 603 hdmi_phy: hdmi-phy@10209100 { 604 compatible = "mediatek,mt8173-hdmi-phy"; 605 reg = <0 0x10209100 0 0x24>; 606 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 607 clock-names = "pll_ref"; 608 clock-output-names = "hdmitx_dig_cts"; 609 mediatek,ibias = <0xa>; 610 mediatek,ibias_up = <0x1c>; 611 #clock-cells = <0>; 612 #phy-cells = <0>; 613 status = "disabled"; 614 }; 615 616 gce: mailbox@10212000 { 617 compatible = "mediatek,mt8173-gce"; 618 reg = <0 0x10212000 0 0x1000>; 619 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 620 clocks = <&infracfg CLK_INFRA_GCE>; 621 clock-names = "gce"; 622 #mbox-cells = <2>; 623 }; 624 625 mipi_tx0: dsi-phy@10215000 { 626 compatible = "mediatek,mt8173-mipi-tx"; 627 reg = <0 0x10215000 0 0x1000>; 628 clocks = <&clk26m>; 629 clock-output-names = "mipi_tx0_pll"; 630 #clock-cells = <0>; 631 #phy-cells = <0>; 632 status = "disabled"; 633 }; 634 635 mipi_tx1: dsi-phy@10216000 { 636 compatible = "mediatek,mt8173-mipi-tx"; 637 reg = <0 0x10216000 0 0x1000>; 638 clocks = <&clk26m>; 639 clock-output-names = "mipi_tx1_pll"; 640 #clock-cells = <0>; 641 #phy-cells = <0>; 642 status = "disabled"; 643 }; 644 645 gic: interrupt-controller@10221000 { 646 compatible = "arm,gic-400"; 647 #interrupt-cells = <3>; 648 interrupt-parent = <&gic>; 649 interrupt-controller; 650 reg = <0 0x10221000 0 0x1000>, 651 <0 0x10222000 0 0x2000>, 652 <0 0x10224000 0 0x2000>, 653 <0 0x10226000 0 0x2000>; 654 interrupts = <GIC_PPI 9 655 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 656 }; 657 658 auxadc: auxadc@11001000 { 659 compatible = "mediatek,mt8173-auxadc"; 660 reg = <0 0x11001000 0 0x1000>; 661 clocks = <&pericfg CLK_PERI_AUXADC>; 662 clock-names = "main"; 663 #io-channel-cells = <1>; 664 }; 665 666 uart0: serial@11002000 { 667 compatible = "mediatek,mt8173-uart", 668 "mediatek,mt6577-uart"; 669 reg = <0 0x11002000 0 0x400>; 670 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 671 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 672 clock-names = "baud", "bus"; 673 status = "disabled"; 674 }; 675 676 uart1: serial@11003000 { 677 compatible = "mediatek,mt8173-uart", 678 "mediatek,mt6577-uart"; 679 reg = <0 0x11003000 0 0x400>; 680 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 681 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 682 clock-names = "baud", "bus"; 683 status = "disabled"; 684 }; 685 686 uart2: serial@11004000 { 687 compatible = "mediatek,mt8173-uart", 688 "mediatek,mt6577-uart"; 689 reg = <0 0x11004000 0 0x400>; 690 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 691 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 692 clock-names = "baud", "bus"; 693 status = "disabled"; 694 }; 695 696 uart3: serial@11005000 { 697 compatible = "mediatek,mt8173-uart", 698 "mediatek,mt6577-uart"; 699 reg = <0 0x11005000 0 0x400>; 700 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 701 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 702 clock-names = "baud", "bus"; 703 status = "disabled"; 704 }; 705 706 i2c0: i2c@11007000 { 707 compatible = "mediatek,mt8173-i2c"; 708 reg = <0 0x11007000 0 0x70>, 709 <0 0x11000100 0 0x80>; 710 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 711 clock-div = <16>; 712 clocks = <&pericfg CLK_PERI_I2C0>, 713 <&pericfg CLK_PERI_AP_DMA>; 714 clock-names = "main", "dma"; 715 pinctrl-names = "default"; 716 pinctrl-0 = <&i2c0_pins_a>; 717 #address-cells = <1>; 718 #size-cells = <0>; 719 status = "disabled"; 720 }; 721 722 i2c1: i2c@11008000 { 723 compatible = "mediatek,mt8173-i2c"; 724 reg = <0 0x11008000 0 0x70>, 725 <0 0x11000180 0 0x80>; 726 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 727 clock-div = <16>; 728 clocks = <&pericfg CLK_PERI_I2C1>, 729 <&pericfg CLK_PERI_AP_DMA>; 730 clock-names = "main", "dma"; 731 pinctrl-names = "default"; 732 pinctrl-0 = <&i2c1_pins_a>; 733 #address-cells = <1>; 734 #size-cells = <0>; 735 status = "disabled"; 736 }; 737 738 i2c2: i2c@11009000 { 739 compatible = "mediatek,mt8173-i2c"; 740 reg = <0 0x11009000 0 0x70>, 741 <0 0x11000200 0 0x80>; 742 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 743 clock-div = <16>; 744 clocks = <&pericfg CLK_PERI_I2C2>, 745 <&pericfg CLK_PERI_AP_DMA>; 746 clock-names = "main", "dma"; 747 pinctrl-names = "default"; 748 pinctrl-0 = <&i2c2_pins_a>; 749 #address-cells = <1>; 750 #size-cells = <0>; 751 status = "disabled"; 752 }; 753 754 spi: spi@1100a000 { 755 compatible = "mediatek,mt8173-spi"; 756 #address-cells = <1>; 757 #size-cells = <0>; 758 reg = <0 0x1100a000 0 0x1000>; 759 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 760 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 761 <&topckgen CLK_TOP_SPI_SEL>, 762 <&pericfg CLK_PERI_SPI0>; 763 clock-names = "parent-clk", "sel-clk", "spi-clk"; 764 status = "disabled"; 765 }; 766 767 thermal: thermal@1100b000 { 768 #thermal-sensor-cells = <0>; 769 compatible = "mediatek,mt8173-thermal"; 770 reg = <0 0x1100b000 0 0x1000>; 771 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 772 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 773 clock-names = "therm", "auxadc"; 774 resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 775 mediatek,auxadc = <&auxadc>; 776 mediatek,apmixedsys = <&apmixedsys>; 777 nvmem-cells = <&thermal_calibration>; 778 nvmem-cell-names = "calibration-data"; 779 }; 780 781 nor_flash: spi@1100d000 { 782 compatible = "mediatek,mt8173-nor"; 783 reg = <0 0x1100d000 0 0xe0>; 784 clocks = <&pericfg CLK_PERI_SPI>, 785 <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 786 clock-names = "spi", "sf"; 787 #address-cells = <1>; 788 #size-cells = <0>; 789 status = "disabled"; 790 }; 791 792 i2c3: i2c@11010000 { 793 compatible = "mediatek,mt8173-i2c"; 794 reg = <0 0x11010000 0 0x70>, 795 <0 0x11000280 0 0x80>; 796 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 797 clock-div = <16>; 798 clocks = <&pericfg CLK_PERI_I2C3>, 799 <&pericfg CLK_PERI_AP_DMA>; 800 clock-names = "main", "dma"; 801 pinctrl-names = "default"; 802 pinctrl-0 = <&i2c3_pins_a>; 803 #address-cells = <1>; 804 #size-cells = <0>; 805 status = "disabled"; 806 }; 807 808 i2c4: i2c@11011000 { 809 compatible = "mediatek,mt8173-i2c"; 810 reg = <0 0x11011000 0 0x70>, 811 <0 0x11000300 0 0x80>; 812 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 813 clock-div = <16>; 814 clocks = <&pericfg CLK_PERI_I2C4>, 815 <&pericfg CLK_PERI_AP_DMA>; 816 clock-names = "main", "dma"; 817 pinctrl-names = "default"; 818 pinctrl-0 = <&i2c4_pins_a>; 819 #address-cells = <1>; 820 #size-cells = <0>; 821 status = "disabled"; 822 }; 823 824 hdmiddc0: i2c@11012000 { 825 compatible = "mediatek,mt8173-hdmi-ddc"; 826 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 827 reg = <0 0x11012000 0 0x1C>; 828 clocks = <&pericfg CLK_PERI_I2C5>; 829 clock-names = "ddc-i2c"; 830 }; 831 832 i2c6: i2c@11013000 { 833 compatible = "mediatek,mt8173-i2c"; 834 reg = <0 0x11013000 0 0x70>, 835 <0 0x11000080 0 0x80>; 836 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 837 clock-div = <16>; 838 clocks = <&pericfg CLK_PERI_I2C6>, 839 <&pericfg CLK_PERI_AP_DMA>; 840 clock-names = "main", "dma"; 841 pinctrl-names = "default"; 842 pinctrl-0 = <&i2c6_pins_a>; 843 #address-cells = <1>; 844 #size-cells = <0>; 845 status = "disabled"; 846 }; 847 848 afe: audio-controller@11220000 { 849 compatible = "mediatek,mt8173-afe-pcm"; 850 reg = <0 0x11220000 0 0x1000>; 851 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 852 power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>; 853 clocks = <&infracfg CLK_INFRA_AUDIO>, 854 <&topckgen CLK_TOP_AUDIO_SEL>, 855 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 856 <&topckgen CLK_TOP_APLL1_DIV0>, 857 <&topckgen CLK_TOP_APLL2_DIV0>, 858 <&topckgen CLK_TOP_I2S0_M_SEL>, 859 <&topckgen CLK_TOP_I2S1_M_SEL>, 860 <&topckgen CLK_TOP_I2S2_M_SEL>, 861 <&topckgen CLK_TOP_I2S3_M_SEL>, 862 <&topckgen CLK_TOP_I2S3_B_SEL>; 863 clock-names = "infra_sys_audio_clk", 864 "top_pdn_audio", 865 "top_pdn_aud_intbus", 866 "bck0", 867 "bck1", 868 "i2s0_m", 869 "i2s1_m", 870 "i2s2_m", 871 "i2s3_m", 872 "i2s3_b"; 873 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 874 <&topckgen CLK_TOP_AUD_2_SEL>; 875 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 876 <&topckgen CLK_TOP_APLL2>; 877 }; 878 879 mmc0: mmc@11230000 { 880 compatible = "mediatek,mt8173-mmc"; 881 reg = <0 0x11230000 0 0x1000>; 882 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 883 clocks = <&pericfg CLK_PERI_MSDC30_0>, 884 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 885 clock-names = "source", "hclk"; 886 status = "disabled"; 887 }; 888 889 mmc1: mmc@11240000 { 890 compatible = "mediatek,mt8173-mmc"; 891 reg = <0 0x11240000 0 0x1000>; 892 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 893 clocks = <&pericfg CLK_PERI_MSDC30_1>, 894 <&topckgen CLK_TOP_AXI_SEL>; 895 clock-names = "source", "hclk"; 896 status = "disabled"; 897 }; 898 899 mmc2: mmc@11250000 { 900 compatible = "mediatek,mt8173-mmc"; 901 reg = <0 0x11250000 0 0x1000>; 902 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 903 clocks = <&pericfg CLK_PERI_MSDC30_2>, 904 <&topckgen CLK_TOP_AXI_SEL>; 905 clock-names = "source", "hclk"; 906 status = "disabled"; 907 }; 908 909 mmc3: mmc@11260000 { 910 compatible = "mediatek,mt8173-mmc"; 911 reg = <0 0x11260000 0 0x1000>; 912 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 913 clocks = <&pericfg CLK_PERI_MSDC30_3>, 914 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 915 clock-names = "source", "hclk"; 916 status = "disabled"; 917 }; 918 919 ssusb: usb@11271000 { 920 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3"; 921 reg = <0 0x11271000 0 0x3000>, 922 <0 0x11280700 0 0x0100>; 923 reg-names = "mac", "ippc"; 924 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>; 925 phys = <&u2port0 PHY_TYPE_USB2>, 926 <&u3port0 PHY_TYPE_USB3>, 927 <&u2port1 PHY_TYPE_USB2>; 928 power-domains = <&spm MT8173_POWER_DOMAIN_USB>; 929 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 930 clock-names = "sys_ck", "ref_ck"; 931 mediatek,syscon-wakeup = <&pericfg 0x400 1>; 932 #address-cells = <2>; 933 #size-cells = <2>; 934 ranges; 935 status = "disabled"; 936 937 usb_host: usb@11270000 { 938 compatible = "mediatek,mt8173-xhci", 939 "mediatek,mtk-xhci"; 940 reg = <0 0x11270000 0 0x1000>; 941 reg-names = "mac"; 942 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 943 power-domains = <&spm MT8173_POWER_DOMAIN_USB>; 944 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 945 clock-names = "sys_ck", "ref_ck"; 946 status = "disabled"; 947 }; 948 }; 949 950 u3phy: t-phy@11290000 { 951 compatible = "mediatek,mt8173-u3phy"; 952 reg = <0 0x11290000 0 0x800>; 953 #address-cells = <2>; 954 #size-cells = <2>; 955 ranges; 956 status = "okay"; 957 958 u2port0: usb-phy@11290800 { 959 reg = <0 0x11290800 0 0x100>; 960 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 961 clock-names = "ref"; 962 #phy-cells = <1>; 963 status = "okay"; 964 }; 965 966 u3port0: usb-phy@11290900 { 967 reg = <0 0x11290900 0 0x700>; 968 clocks = <&clk26m>; 969 clock-names = "ref"; 970 #phy-cells = <1>; 971 status = "okay"; 972 }; 973 974 u2port1: usb-phy@11291000 { 975 reg = <0 0x11291000 0 0x100>; 976 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 977 clock-names = "ref"; 978 #phy-cells = <1>; 979 status = "okay"; 980 }; 981 }; 982 983 mmsys: syscon@14000000 { 984 compatible = "mediatek,mt8173-mmsys", "syscon"; 985 reg = <0 0x14000000 0 0x1000>; 986 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 987 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 988 assigned-clock-rates = <400000000>; 989 #clock-cells = <1>; 990 #reset-cells = <1>; 991 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 992 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 993 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 994 }; 995 996 mdp_rdma0: rdma@14001000 { 997 compatible = "mediatek,mt8173-mdp-rdma", 998 "mediatek,mt8173-mdp"; 999 reg = <0 0x14001000 0 0x1000>; 1000 clocks = <&mmsys CLK_MM_MDP_RDMA0>, 1001 <&mmsys CLK_MM_MUTEX_32K>; 1002 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1003 iommus = <&iommu M4U_PORT_MDP_RDMA0>; 1004 mediatek,larb = <&larb0>; 1005 mediatek,vpu = <&vpu>; 1006 }; 1007 1008 mdp_rdma1: rdma@14002000 { 1009 compatible = "mediatek,mt8173-mdp-rdma"; 1010 reg = <0 0x14002000 0 0x1000>; 1011 clocks = <&mmsys CLK_MM_MDP_RDMA1>, 1012 <&mmsys CLK_MM_MUTEX_32K>; 1013 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1014 iommus = <&iommu M4U_PORT_MDP_RDMA1>; 1015 mediatek,larb = <&larb4>; 1016 }; 1017 1018 mdp_rsz0: rsz@14003000 { 1019 compatible = "mediatek,mt8173-mdp-rsz"; 1020 reg = <0 0x14003000 0 0x1000>; 1021 clocks = <&mmsys CLK_MM_MDP_RSZ0>; 1022 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1023 }; 1024 1025 mdp_rsz1: rsz@14004000 { 1026 compatible = "mediatek,mt8173-mdp-rsz"; 1027 reg = <0 0x14004000 0 0x1000>; 1028 clocks = <&mmsys CLK_MM_MDP_RSZ1>; 1029 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1030 }; 1031 1032 mdp_rsz2: rsz@14005000 { 1033 compatible = "mediatek,mt8173-mdp-rsz"; 1034 reg = <0 0x14005000 0 0x1000>; 1035 clocks = <&mmsys CLK_MM_MDP_RSZ2>; 1036 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1037 }; 1038 1039 mdp_wdma0: wdma@14006000 { 1040 compatible = "mediatek,mt8173-mdp-wdma"; 1041 reg = <0 0x14006000 0 0x1000>; 1042 clocks = <&mmsys CLK_MM_MDP_WDMA>; 1043 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1044 iommus = <&iommu M4U_PORT_MDP_WDMA>; 1045 mediatek,larb = <&larb0>; 1046 }; 1047 1048 mdp_wrot0: wrot@14007000 { 1049 compatible = "mediatek,mt8173-mdp-wrot"; 1050 reg = <0 0x14007000 0 0x1000>; 1051 clocks = <&mmsys CLK_MM_MDP_WROT0>; 1052 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1053 iommus = <&iommu M4U_PORT_MDP_WROT0>; 1054 mediatek,larb = <&larb0>; 1055 }; 1056 1057 mdp_wrot1: wrot@14008000 { 1058 compatible = "mediatek,mt8173-mdp-wrot"; 1059 reg = <0 0x14008000 0 0x1000>; 1060 clocks = <&mmsys CLK_MM_MDP_WROT1>; 1061 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1062 iommus = <&iommu M4U_PORT_MDP_WROT1>; 1063 mediatek,larb = <&larb4>; 1064 }; 1065 1066 ovl0: ovl@1400c000 { 1067 compatible = "mediatek,mt8173-disp-ovl"; 1068 reg = <0 0x1400c000 0 0x1000>; 1069 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 1070 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1071 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1072 iommus = <&iommu M4U_PORT_DISP_OVL0>; 1073 mediatek,larb = <&larb0>; 1074 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1075 }; 1076 1077 ovl1: ovl@1400d000 { 1078 compatible = "mediatek,mt8173-disp-ovl"; 1079 reg = <0 0x1400d000 0 0x1000>; 1080 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 1081 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1082 clocks = <&mmsys CLK_MM_DISP_OVL1>; 1083 iommus = <&iommu M4U_PORT_DISP_OVL1>; 1084 mediatek,larb = <&larb4>; 1085 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1086 }; 1087 1088 rdma0: rdma@1400e000 { 1089 compatible = "mediatek,mt8173-disp-rdma"; 1090 reg = <0 0x1400e000 0 0x1000>; 1091 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 1092 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1093 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1094 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 1095 mediatek,larb = <&larb0>; 1096 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1097 }; 1098 1099 rdma1: rdma@1400f000 { 1100 compatible = "mediatek,mt8173-disp-rdma"; 1101 reg = <0 0x1400f000 0 0x1000>; 1102 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 1103 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1104 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1105 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1106 mediatek,larb = <&larb4>; 1107 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1108 }; 1109 1110 rdma2: rdma@14010000 { 1111 compatible = "mediatek,mt8173-disp-rdma"; 1112 reg = <0 0x14010000 0 0x1000>; 1113 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 1114 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1115 clocks = <&mmsys CLK_MM_DISP_RDMA2>; 1116 iommus = <&iommu M4U_PORT_DISP_RDMA2>; 1117 mediatek,larb = <&larb4>; 1118 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; 1119 }; 1120 1121 wdma0: wdma@14011000 { 1122 compatible = "mediatek,mt8173-disp-wdma"; 1123 reg = <0 0x14011000 0 0x1000>; 1124 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 1125 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1126 clocks = <&mmsys CLK_MM_DISP_WDMA0>; 1127 iommus = <&iommu M4U_PORT_DISP_WDMA0>; 1128 mediatek,larb = <&larb0>; 1129 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1130 }; 1131 1132 wdma1: wdma@14012000 { 1133 compatible = "mediatek,mt8173-disp-wdma"; 1134 reg = <0 0x14012000 0 0x1000>; 1135 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 1136 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1137 clocks = <&mmsys CLK_MM_DISP_WDMA1>; 1138 iommus = <&iommu M4U_PORT_DISP_WDMA1>; 1139 mediatek,larb = <&larb4>; 1140 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; 1141 }; 1142 1143 color0: color@14013000 { 1144 compatible = "mediatek,mt8173-disp-color"; 1145 reg = <0 0x14013000 0 0x1000>; 1146 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 1147 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1148 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1149 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; 1150 }; 1151 1152 color1: color@14014000 { 1153 compatible = "mediatek,mt8173-disp-color"; 1154 reg = <0 0x14014000 0 0x1000>; 1155 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 1156 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1157 clocks = <&mmsys CLK_MM_DISP_COLOR1>; 1158 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; 1159 }; 1160 1161 aal@14015000 { 1162 compatible = "mediatek,mt8173-disp-aal"; 1163 reg = <0 0x14015000 0 0x1000>; 1164 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 1165 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1166 clocks = <&mmsys CLK_MM_DISP_AAL>; 1167 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; 1168 }; 1169 1170 gamma@14016000 { 1171 compatible = "mediatek,mt8173-disp-gamma"; 1172 reg = <0 0x14016000 0 0x1000>; 1173 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 1174 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1175 clocks = <&mmsys CLK_MM_DISP_GAMMA>; 1176 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; 1177 }; 1178 1179 merge@14017000 { 1180 compatible = "mediatek,mt8173-disp-merge"; 1181 reg = <0 0x14017000 0 0x1000>; 1182 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1183 clocks = <&mmsys CLK_MM_DISP_MERGE>; 1184 }; 1185 1186 split0: split@14018000 { 1187 compatible = "mediatek,mt8173-disp-split"; 1188 reg = <0 0x14018000 0 0x1000>; 1189 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1190 clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 1191 }; 1192 1193 split1: split@14019000 { 1194 compatible = "mediatek,mt8173-disp-split"; 1195 reg = <0 0x14019000 0 0x1000>; 1196 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1197 clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 1198 }; 1199 1200 ufoe@1401a000 { 1201 compatible = "mediatek,mt8173-disp-ufoe"; 1202 reg = <0 0x1401a000 0 0x1000>; 1203 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 1204 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1205 clocks = <&mmsys CLK_MM_DISP_UFOE>; 1206 }; 1207 1208 dsi0: dsi@1401b000 { 1209 compatible = "mediatek,mt8173-dsi"; 1210 reg = <0 0x1401b000 0 0x1000>; 1211 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 1212 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1213 clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 1214 <&mmsys CLK_MM_DSI0_DIGITAL>, 1215 <&mipi_tx0>; 1216 clock-names = "engine", "digital", "hs"; 1217 resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; 1218 phys = <&mipi_tx0>; 1219 phy-names = "dphy"; 1220 status = "disabled"; 1221 }; 1222 1223 dsi1: dsi@1401c000 { 1224 compatible = "mediatek,mt8173-dsi"; 1225 reg = <0 0x1401c000 0 0x1000>; 1226 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 1227 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1228 clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 1229 <&mmsys CLK_MM_DSI1_DIGITAL>, 1230 <&mipi_tx1>; 1231 clock-names = "engine", "digital", "hs"; 1232 phys = <&mipi_tx1>; 1233 phy-names = "dphy"; 1234 status = "disabled"; 1235 }; 1236 1237 dpi0: dpi@1401d000 { 1238 compatible = "mediatek,mt8173-dpi"; 1239 reg = <0 0x1401d000 0 0x1000>; 1240 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 1241 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1242 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 1243 <&mmsys CLK_MM_DPI_ENGINE>, 1244 <&apmixedsys CLK_APMIXED_TVDPLL>; 1245 clock-names = "pixel", "engine", "pll"; 1246 status = "disabled"; 1247 1248 port { 1249 dpi0_out: endpoint { 1250 remote-endpoint = <&hdmi0_in>; 1251 }; 1252 }; 1253 }; 1254 1255 pwm0: pwm@1401e000 { 1256 compatible = "mediatek,mt8173-disp-pwm", 1257 "mediatek,mt6595-disp-pwm"; 1258 reg = <0 0x1401e000 0 0x1000>; 1259 #pwm-cells = <2>; 1260 clocks = <&mmsys CLK_MM_DISP_PWM026M>, 1261 <&mmsys CLK_MM_DISP_PWM0MM>; 1262 clock-names = "main", "mm"; 1263 status = "disabled"; 1264 }; 1265 1266 pwm1: pwm@1401f000 { 1267 compatible = "mediatek,mt8173-disp-pwm", 1268 "mediatek,mt6595-disp-pwm"; 1269 reg = <0 0x1401f000 0 0x1000>; 1270 #pwm-cells = <2>; 1271 clocks = <&mmsys CLK_MM_DISP_PWM126M>, 1272 <&mmsys CLK_MM_DISP_PWM1MM>; 1273 clock-names = "main", "mm"; 1274 status = "disabled"; 1275 }; 1276 1277 mutex: mutex@14020000 { 1278 compatible = "mediatek,mt8173-disp-mutex"; 1279 reg = <0 0x14020000 0 0x1000>; 1280 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 1281 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1282 clocks = <&mmsys CLK_MM_MUTEX_32K>; 1283 mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>, 1284 <CMDQ_EVENT_MUTEX1_STREAM_EOF>; 1285 }; 1286 1287 larb0: larb@14021000 { 1288 compatible = "mediatek,mt8173-smi-larb"; 1289 reg = <0 0x14021000 0 0x1000>; 1290 mediatek,smi = <&smi_common>; 1291 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1292 clocks = <&mmsys CLK_MM_SMI_LARB0>, 1293 <&mmsys CLK_MM_SMI_LARB0>; 1294 clock-names = "apb", "smi"; 1295 }; 1296 1297 smi_common: smi@14022000 { 1298 compatible = "mediatek,mt8173-smi-common"; 1299 reg = <0 0x14022000 0 0x1000>; 1300 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1301 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1302 <&mmsys CLK_MM_SMI_COMMON>; 1303 clock-names = "apb", "smi"; 1304 }; 1305 1306 od@14023000 { 1307 compatible = "mediatek,mt8173-disp-od"; 1308 reg = <0 0x14023000 0 0x1000>; 1309 clocks = <&mmsys CLK_MM_DISP_OD>; 1310 }; 1311 1312 hdmi0: hdmi@14025000 { 1313 compatible = "mediatek,mt8173-hdmi"; 1314 reg = <0 0x14025000 0 0x400>; 1315 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 1316 clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 1317 <&mmsys CLK_MM_HDMI_PLLCK>, 1318 <&mmsys CLK_MM_HDMI_AUDIO>, 1319 <&mmsys CLK_MM_HDMI_SPDIF>; 1320 clock-names = "pixel", "pll", "bclk", "spdif"; 1321 pinctrl-names = "default"; 1322 pinctrl-0 = <&hdmi_pin>; 1323 phys = <&hdmi_phy>; 1324 phy-names = "hdmi"; 1325 mediatek,syscon-hdmi = <&mmsys 0x900>; 1326 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1327 assigned-clock-parents = <&hdmi_phy>; 1328 status = "disabled"; 1329 1330 ports { 1331 #address-cells = <1>; 1332 #size-cells = <0>; 1333 1334 port@0 { 1335 reg = <0>; 1336 1337 hdmi0_in: endpoint { 1338 remote-endpoint = <&dpi0_out>; 1339 }; 1340 }; 1341 }; 1342 }; 1343 1344 larb4: larb@14027000 { 1345 compatible = "mediatek,mt8173-smi-larb"; 1346 reg = <0 0x14027000 0 0x1000>; 1347 mediatek,smi = <&smi_common>; 1348 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1349 clocks = <&mmsys CLK_MM_SMI_LARB4>, 1350 <&mmsys CLK_MM_SMI_LARB4>; 1351 clock-names = "apb", "smi"; 1352 }; 1353 1354 imgsys: clock-controller@15000000 { 1355 compatible = "mediatek,mt8173-imgsys", "syscon"; 1356 reg = <0 0x15000000 0 0x1000>; 1357 #clock-cells = <1>; 1358 }; 1359 1360 larb2: larb@15001000 { 1361 compatible = "mediatek,mt8173-smi-larb"; 1362 reg = <0 0x15001000 0 0x1000>; 1363 mediatek,smi = <&smi_common>; 1364 power-domains = <&spm MT8173_POWER_DOMAIN_ISP>; 1365 clocks = <&imgsys CLK_IMG_LARB2_SMI>, 1366 <&imgsys CLK_IMG_LARB2_SMI>; 1367 clock-names = "apb", "smi"; 1368 }; 1369 1370 vdecsys: clock-controller@16000000 { 1371 compatible = "mediatek,mt8173-vdecsys", "syscon"; 1372 reg = <0 0x16000000 0 0x1000>; 1373 #clock-cells = <1>; 1374 }; 1375 1376 vcodec_dec: vcodec@16000000 { 1377 compatible = "mediatek,mt8173-vcodec-dec"; 1378 reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ 1379 <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 1380 <0 0x16021000 0 0x800>, /* VDEC_LD */ 1381 <0 0x16021800 0 0x800>, /* VDEC_TOP */ 1382 <0 0x16022000 0 0x1000>, /* VDEC_CM */ 1383 <0 0x16023000 0 0x1000>, /* VDEC_AD */ 1384 <0 0x16024000 0 0x1000>, /* VDEC_AV */ 1385 <0 0x16025000 0 0x1000>, /* VDEC_PP */ 1386 <0 0x16026800 0 0x800>, /* VDEC_HWD */ 1387 <0 0x16027000 0 0x800>, /* VDEC_HWQ */ 1388 <0 0x16027800 0 0x800>, /* VDEC_HWB */ 1389 <0 0x16028400 0 0x400>; /* VDEC_HWG */ 1390 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 1391 mediatek,larb = <&larb1>; 1392 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 1393 <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 1394 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 1395 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 1396 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 1397 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, 1398 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 1399 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; 1400 mediatek,vpu = <&vpu>; 1401 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>; 1402 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, 1403 <&topckgen CLK_TOP_UNIVPLL_D2>, 1404 <&topckgen CLK_TOP_CCI400_SEL>, 1405 <&topckgen CLK_TOP_VDEC_SEL>, 1406 <&topckgen CLK_TOP_VCODECPLL>, 1407 <&apmixedsys CLK_APMIXED_VENCPLL>, 1408 <&topckgen CLK_TOP_VENC_LT_SEL>, 1409 <&topckgen CLK_TOP_VCODECPLL_370P5>; 1410 clock-names = "vcodecpll", 1411 "univpll_d2", 1412 "clk_cci400_sel", 1413 "vdec_sel", 1414 "vdecpll", 1415 "vencpll", 1416 "venc_lt_sel", 1417 "vdec_bus_clk_src"; 1418 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, 1419 <&topckgen CLK_TOP_CCI400_SEL>, 1420 <&topckgen CLK_TOP_VDEC_SEL>, 1421 <&apmixedsys CLK_APMIXED_VCODECPLL>, 1422 <&apmixedsys CLK_APMIXED_VENCPLL>; 1423 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, 1424 <&topckgen CLK_TOP_UNIVPLL_D2>, 1425 <&topckgen CLK_TOP_VCODECPLL>; 1426 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; 1427 }; 1428 1429 larb1: larb@16010000 { 1430 compatible = "mediatek,mt8173-smi-larb"; 1431 reg = <0 0x16010000 0 0x1000>; 1432 mediatek,smi = <&smi_common>; 1433 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>; 1434 clocks = <&vdecsys CLK_VDEC_CKEN>, 1435 <&vdecsys CLK_VDEC_LARB_CKEN>; 1436 clock-names = "apb", "smi"; 1437 }; 1438 1439 vencsys: clock-controller@18000000 { 1440 compatible = "mediatek,mt8173-vencsys", "syscon"; 1441 reg = <0 0x18000000 0 0x1000>; 1442 #clock-cells = <1>; 1443 }; 1444 1445 larb3: larb@18001000 { 1446 compatible = "mediatek,mt8173-smi-larb"; 1447 reg = <0 0x18001000 0 0x1000>; 1448 mediatek,smi = <&smi_common>; 1449 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; 1450 clocks = <&vencsys CLK_VENC_CKE1>, 1451 <&vencsys CLK_VENC_CKE0>; 1452 clock-names = "apb", "smi"; 1453 }; 1454 1455 vcodec_enc_avc: vcodec@18002000 { 1456 compatible = "mediatek,mt8173-vcodec-enc"; 1457 reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */ 1458 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; 1459 mediatek,larb = <&larb3>; 1460 iommus = <&iommu M4U_PORT_VENC_RCPU>, 1461 <&iommu M4U_PORT_VENC_REC>, 1462 <&iommu M4U_PORT_VENC_BSDMA>, 1463 <&iommu M4U_PORT_VENC_SV_COMV>, 1464 <&iommu M4U_PORT_VENC_RD_COMV>, 1465 <&iommu M4U_PORT_VENC_CUR_LUMA>, 1466 <&iommu M4U_PORT_VENC_CUR_CHROMA>, 1467 <&iommu M4U_PORT_VENC_REF_LUMA>, 1468 <&iommu M4U_PORT_VENC_REF_CHROMA>, 1469 <&iommu M4U_PORT_VENC_NBM_RDMA>, 1470 <&iommu M4U_PORT_VENC_NBM_WDMA>; 1471 mediatek,vpu = <&vpu>; 1472 clocks = <&topckgen CLK_TOP_VENC_SEL>; 1473 clock-names = "venc_sel"; 1474 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; 1475 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; 1476 }; 1477 1478 jpegdec: jpegdec@18004000 { 1479 compatible = "mediatek,mt8173-jpgdec"; 1480 reg = <0 0x18004000 0 0x1000>; 1481 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>; 1482 clocks = <&vencsys CLK_VENC_CKE0>, 1483 <&vencsys CLK_VENC_CKE3>; 1484 clock-names = "jpgdec-smi", 1485 "jpgdec"; 1486 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; 1487 mediatek,larb = <&larb3>; 1488 iommus = <&iommu M4U_PORT_JPGDEC_WDMA>, 1489 <&iommu M4U_PORT_JPGDEC_BSDMA>; 1490 }; 1491 1492 vencltsys: clock-controller@19000000 { 1493 compatible = "mediatek,mt8173-vencltsys", "syscon"; 1494 reg = <0 0x19000000 0 0x1000>; 1495 #clock-cells = <1>; 1496 }; 1497 1498 larb5: larb@19001000 { 1499 compatible = "mediatek,mt8173-smi-larb"; 1500 reg = <0 0x19001000 0 0x1000>; 1501 mediatek,smi = <&smi_common>; 1502 power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>; 1503 clocks = <&vencltsys CLK_VENCLT_CKE1>, 1504 <&vencltsys CLK_VENCLT_CKE0>; 1505 clock-names = "apb", "smi"; 1506 }; 1507 1508 vcodec_enc_vp8: vcodec@19002000 { 1509 compatible = "mediatek,mt8173-vcodec-enc-vp8"; 1510 reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 1511 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 1512 iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, 1513 <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 1514 <&iommu M4U_PORT_VENC_BSDMA_SET2>, 1515 <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 1516 <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 1517 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 1518 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 1519 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 1520 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 1521 mediatek,larb = <&larb5>; 1522 mediatek,vpu = <&vpu>; 1523 clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; 1524 clock-names = "venc_lt_sel"; 1525 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; 1526 assigned-clock-parents = 1527 <&topckgen CLK_TOP_VCODECPLL_370P5>; 1528 }; 1529 }; 1530}; 1531