1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Source for the TMPV7708 4 * 5 * (C) Copyright 2018 - 2020, Toshiba Corporation. 6 * (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> 7 * 8 */ 9 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12 13/memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */ 14 15/ { 16 compatible = "toshiba,tmpv7708"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu-map { 25 cluster0 { 26 core0 { 27 cpu = <&cpu0>; 28 }; 29 core1 { 30 cpu = <&cpu1>; 31 }; 32 core2 { 33 cpu = <&cpu2>; 34 }; 35 core3 { 36 cpu = <&cpu3>; 37 }; 38 }; 39 40 cluster1 { 41 core0 { 42 cpu = <&cpu4>; 43 }; 44 core1 { 45 cpu = <&cpu5>; 46 }; 47 core2 { 48 cpu = <&cpu6>; 49 }; 50 core3 { 51 cpu = <&cpu7>; 52 }; 53 }; 54 }; 55 56 cpu0: cpu@0 { 57 compatible = "arm,cortex-a53"; 58 device_type = "cpu"; 59 enable-method = "spin-table"; 60 cpu-release-addr = <0x0 0x81100000>; 61 reg = <0x00>; 62 }; 63 64 cpu1: cpu@1 { 65 compatible = "arm,cortex-a53"; 66 device_type = "cpu"; 67 enable-method = "spin-table"; 68 cpu-release-addr = <0x0 0x81100000>; 69 reg = <0x01>; 70 }; 71 72 cpu2: cpu@2 { 73 compatible = "arm,cortex-a53"; 74 device_type = "cpu"; 75 enable-method = "spin-table"; 76 cpu-release-addr = <0x0 0x81100000>; 77 reg = <0x02>; 78 }; 79 80 cpu3: cpu@3 { 81 compatible = "arm,cortex-a53"; 82 device_type = "cpu"; 83 enable-method = "spin-table"; 84 cpu-release-addr = <0x0 0x81100000>; 85 reg = <0x03>; 86 }; 87 88 cpu4: cpu@100 { 89 compatible = "arm,cortex-a53"; 90 device_type = "cpu"; 91 enable-method = "spin-table"; 92 cpu-release-addr = <0x0 0x81100000>; 93 reg = <0x100>; 94 }; 95 96 cpu5: cpu@101 { 97 compatible = "arm,cortex-a53"; 98 device_type = "cpu"; 99 enable-method = "spin-table"; 100 cpu-release-addr = <0x0 0x81100000>; 101 reg = <0x101>; 102 }; 103 104 cpu6: cpu@102 { 105 compatible = "arm,cortex-a53"; 106 device_type = "cpu"; 107 enable-method = "spin-table"; 108 cpu-release-addr = <0x0 0x81100000>; 109 reg = <0x102>; 110 }; 111 112 cpu7: cpu@103 { 113 compatible = "arm,cortex-a53"; 114 device_type = "cpu"; 115 enable-method = "spin-table"; 116 cpu-release-addr = <0x0 0x81100000>; 117 reg = <0x103>; 118 }; 119 }; 120 121 timer { 122 compatible = "arm,armv8-timer"; 123 interrupt-parent = <&gic>; 124 interrupts = 125 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 126 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 127 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 128 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 129 }; 130 131 uart_clk: uart-clk { 132 compatible = "fixed-clock"; 133 clock-frequency = <150000000>; 134 #clock-cells = <0>; 135 }; 136 137 clk25mhz: clk25mhz { 138 compatible = "fixed-clock"; 139 #clock-cells = <0>; 140 clock-frequency = <25000000>; 141 clock-output-names = "clk25mhz"; 142 }; 143 144 clk125mhz: clk125mhz { 145 compatible = "fixed-clock"; 146 clock-frequency = <125000000>; 147 #clock-cells = <0>; 148 clock-output-names = "clk125mhz"; 149 }; 150 151 clk150mhz: clk150mhz { 152 compatible = "fixed-clock"; 153 clock-frequency = <150000000>; 154 #clock-cells = <0>; 155 clock-output-names = "clk150mhz"; 156 }; 157 158 clk300mhz: clk300mhz { 159 compatible = "fixed-clock"; 160 clock-frequency = <300000000>; 161 #clock-cells = <0>; 162 clock-output-names = "clk300mhz"; 163 }; 164 165 clk600mhz: clk600mhz { 166 compatible = "fixed-clock"; 167 #clock-cells = <0>; 168 clock-frequency = <600000000>; 169 clock-output-names = "clk600mhz"; 170 }; 171 172 extclk100mhz: extclk100mhz { 173 compatible = "fixed-clock"; 174 #clock-cells = <0>; 175 clock-frequency = <100000000>; 176 clock-output-names = "extclk100mhz"; 177 }; 178 179 wdt_clk: wdt-clk { 180 compatible = "fixed-clock"; 181 clock-frequency = <150000000>; 182 #clock-cells = <0>; 183 }; 184 185 soc { 186 #address-cells = <2>; 187 #size-cells = <2>; 188 compatible = "simple-bus"; 189 interrupt-parent = <&gic>; 190 ranges; 191 192 gic: interrupt-controller@24001000 { 193 compatible = "arm,gic-400"; 194 interrupt-controller; 195 #interrupt-cells = <3>; 196 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 197 reg = <0 0x24001000 0 0x1000>, 198 <0 0x24002000 0 0x2000>, 199 <0 0x24004000 0 0x2000>, 200 <0 0x24006000 0 0x2000>; 201 }; 202 203 pmux: pmux@24190000 { 204 compatible = "toshiba,tmpv7708-pinctrl"; 205 reg = <0 0x24190000 0 0x10000>; 206 }; 207 208 gpio: gpio@28020000 { 209 compatible = "toshiba,gpio-tmpv7708"; 210 reg = <0 0x28020000 0 0x1000>; 211 #gpio-cells = <0x2>; 212 gpio-ranges = <&pmux 0 0 32>; 213 gpio-controller; 214 interrupt-controller; 215 #interrupt-cells = <2>; 216 interrupt-parent = <&gic>; 217 }; 218 219 uart0: serial@28200000 { 220 compatible = "arm,pl011", "arm,primecell"; 221 reg = <0 0x28200000 0 0x1000>; 222 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 223 pinctrl-names = "default"; 224 pinctrl-0 = <&uart0_pins>; 225 status = "disabled"; 226 }; 227 228 uart1: serial@28201000 { 229 compatible = "arm,pl011", "arm,primecell"; 230 reg = <0 0x28201000 0 0x1000>; 231 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 232 pinctrl-names = "default"; 233 pinctrl-0 = <&uart1_pins>; 234 status = "disabled"; 235 }; 236 237 uart2: serial@28202000 { 238 compatible = "arm,pl011", "arm,primecell"; 239 reg = <0 0x28202000 0 0x1000>; 240 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 241 pinctrl-names = "default"; 242 pinctrl-0 = <&uart2_pins>; 243 status = "disabled"; 244 }; 245 246 uart3: serial@28203000 { 247 compatible = "arm,pl011", "arm,primecell"; 248 reg = <0 0x28203000 0 0x1000>; 249 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 250 pinctrl-names = "default"; 251 pinctrl-0 = <&uart3_pins>; 252 status = "disabled"; 253 }; 254 255 i2c0: i2c@28030000 { 256 compatible = "snps,designware-i2c"; 257 reg = <0 0x28030000 0 0x1000>; 258 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 259 pinctrl-names = "default"; 260 pinctrl-0 = <&i2c0_pins>; 261 clock-frequency = <400000>; 262 #address-cells = <1>; 263 #size-cells = <0>; 264 status = "disabled"; 265 }; 266 267 i2c1: i2c@28031000 { 268 compatible = "snps,designware-i2c"; 269 reg = <0 0x28031000 0 0x1000>; 270 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 271 pinctrl-names = "default"; 272 pinctrl-0 = <&i2c1_pins>; 273 clock-frequency = <400000>; 274 #address-cells = <1>; 275 #size-cells = <0>; 276 status = "disabled"; 277 }; 278 279 i2c2: i2c@28032000 { 280 compatible = "snps,designware-i2c"; 281 reg = <0 0x28032000 0 0x1000>; 282 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&i2c2_pins>; 285 clock-frequency = <400000>; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 status = "disabled"; 289 }; 290 291 i2c3: i2c@28033000 { 292 compatible = "snps,designware-i2c"; 293 reg = <0 0x28033000 0 0x1000>; 294 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&i2c3_pins>; 297 clock-frequency = <400000>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 status = "disabled"; 301 }; 302 303 i2c4: i2c@28034000 { 304 compatible = "snps,designware-i2c"; 305 reg = <0 0x28034000 0 0x1000>; 306 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&i2c4_pins>; 309 clock-frequency = <400000>; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 status = "disabled"; 313 }; 314 315 i2c5: i2c@28035000 { 316 compatible = "snps,designware-i2c"; 317 reg = <0 0x28035000 0 0x1000>; 318 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 319 pinctrl-names = "default"; 320 pinctrl-0 = <&i2c5_pins>; 321 clock-frequency = <400000>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 status = "disabled"; 325 }; 326 327 i2c6: i2c@28036000 { 328 compatible = "snps,designware-i2c"; 329 reg = <0 0x28036000 0 0x1000>; 330 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 331 pinctrl-names = "default"; 332 pinctrl-0 = <&i2c6_pins>; 333 clock-frequency = <400000>; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 status = "disabled"; 337 }; 338 339 i2c7: i2c@28037000 { 340 compatible = "snps,designware-i2c"; 341 reg = <0 0x28037000 0 0x1000>; 342 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 343 pinctrl-names = "default"; 344 pinctrl-0 = <&i2c7_pins>; 345 clock-frequency = <400000>; 346 #address-cells = <1>; 347 #size-cells = <0>; 348 status = "disabled"; 349 }; 350 351 i2c8: i2c@28038000 { 352 compatible = "snps,designware-i2c"; 353 reg = <0 0x28038000 0 0x1000>; 354 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 355 pinctrl-names = "default"; 356 pinctrl-0 = <&i2c8_pins>; 357 clock-frequency = <400000>; 358 #address-cells = <1>; 359 #size-cells = <0>; 360 status = "disabled"; 361 }; 362 363 spi0: spi@28140000 { 364 compatible = "arm,pl022", "arm,primecell"; 365 reg = <0 0x28140000 0 0x1000>; 366 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 367 pinctrl-names = "default"; 368 pinctrl-0 = <&spi0_pins>; 369 num-cs = <1>; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 status = "disabled"; 373 }; 374 375 spi1: spi@28141000 { 376 compatible = "arm,pl022", "arm,primecell"; 377 reg = <0 0x28141000 0 0x1000>; 378 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 379 pinctrl-names = "default"; 380 pinctrl-0 = <&spi1_pins>; 381 num-cs = <1>; 382 #address-cells = <1>; 383 #size-cells = <0>; 384 status = "disabled"; 385 }; 386 387 spi2: spi@28142000 { 388 compatible = "arm,pl022", "arm,primecell"; 389 reg = <0 0x28142000 0 0x1000>; 390 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 391 pinctrl-names = "default"; 392 pinctrl-0 = <&spi2_pins>; 393 num-cs = <1>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 status = "disabled"; 397 }; 398 399 spi3: spi@28143000 { 400 compatible = "arm,pl022", "arm,primecell"; 401 reg = <0 0x28143000 0 0x1000>; 402 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 403 pinctrl-names = "default"; 404 pinctrl-0 = <&spi3_pins>; 405 num-cs = <1>; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 status = "disabled"; 409 }; 410 411 spi4: spi@28144000 { 412 compatible = "arm,pl022", "arm,primecell"; 413 reg = <0 0x28144000 0 0x1000>; 414 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 415 pinctrl-names = "default"; 416 pinctrl-0 = <&spi4_pins>; 417 num-cs = <1>; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 status = "disabled"; 421 }; 422 423 spi5: spi@28145000 { 424 compatible = "arm,pl022", "arm,primecell"; 425 reg = <0 0x28145000 0 0x1000>; 426 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 427 pinctrl-names = "default"; 428 pinctrl-0 = <&spi5_pins>; 429 num-cs = <1>; 430 #address-cells = <1>; 431 #size-cells = <0>; 432 status = "disabled"; 433 }; 434 435 spi6: spi@28146000 { 436 compatible = "arm,pl022", "arm,primecell"; 437 reg = <0 0x28146000 0 0x1000>; 438 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 439 pinctrl-names = "default"; 440 pinctrl-0 = <&spi6_pins>; 441 num-cs = <1>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 status = "disabled"; 445 }; 446 447 piether: ethernet@28000000 { 448 compatible = "toshiba,visconti-dwmac", "snps,dwmac-4.20a"; 449 reg = <0 0x28000000 0 0x10000>; 450 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 451 interrupt-names = "macirq"; 452 snps,txpbl = <4>; 453 snps,rxpbl = <4>; 454 snps,tso; 455 status = "disabled"; 456 }; 457 458 wdt: wdt@28330000 { 459 compatible = "toshiba,visconti-wdt"; 460 reg = <0 0x28330000 0 0x1000>; 461 status = "disabled"; 462 }; 463 464 pwm: pwm@241c0000 { 465 compatible = "toshiba,visconti-pwm"; 466 reg = <0 0x241c0000 0 0x1000>; 467 pinctrl-names = "default"; 468 pinctrl-0 = <&pwm_mux>; 469 #pwm-cells = <2>; 470 status = "disabled"; 471 }; 472 473 pcie: pcie@28400000 { 474 compatible = "toshiba,visconti-pcie"; 475 reg = <0x0 0x28400000 0x0 0x00400000>, 476 <0x0 0x70000000 0x0 0x10000000>, 477 <0x0 0x28050000 0x0 0x00010000>, 478 <0x0 0x24200000 0x0 0x00002000>, 479 <0x0 0x24162000 0x0 0x00001000>; 480 reg-names = "dbi", "config", "ulreg", "smu", "mpu"; 481 device_type = "pci"; 482 bus-range = <0x00 0xff>; 483 num-lanes = <2>; 484 num-viewport = <8>; 485 486 #address-cells = <3>; 487 #size-cells = <2>; 488 #interrupt-cells = <1>; 489 ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000 490 0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>; 491 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 493 interrupt-names = "msi", "intr"; 494 interrupt-map-mask = <0 0 0 7>; 495 interrupt-map = 496 <0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 497 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 498 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 499 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 500 max-link-speed = <2>; 501 status = "disabled"; 502 }; 503 }; 504}; 505 506#include "tmpv7708_pins.dtsi" 507