1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /*
3  * Copyright (C) 2012,2013 - ARM Ltd
4  * Author: Marc Zyngier <marc.zyngier@arm.com>
5  *
6  * Derived from arch/arm/include/uapi/asm/kvm.h:
7  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8  * Author: Christoffer Dall <c.dall@virtualopensystems.com>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
21  */
22 
23 #ifndef __ARM_KVM_H__
24 #define __ARM_KVM_H__
25 
26 #define KVM_SPSR_EL1	0
27 #define KVM_SPSR_SVC	KVM_SPSR_EL1
28 #define KVM_SPSR_ABT	1
29 #define KVM_SPSR_UND	2
30 #define KVM_SPSR_IRQ	3
31 #define KVM_SPSR_FIQ	4
32 #define KVM_NR_SPSR	5
33 
34 #ifndef __ASSEMBLY__
35 #include <linux/psci.h>
36 #include <linux/types.h>
37 #include <asm/ptrace.h>
38 #include <asm/sve_context.h>
39 
40 #define __KVM_HAVE_GUEST_DEBUG
41 #define __KVM_HAVE_IRQ_LINE
42 #define __KVM_HAVE_READONLY_MEM
43 #define __KVM_HAVE_VCPU_EVENTS
44 
45 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
46 
47 #define KVM_REG_SIZE(id)						\
48 	(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
49 
50 struct kvm_regs {
51 	struct user_pt_regs regs;	/* sp = sp_el0 */
52 
53 	__u64	sp_el1;
54 	__u64	elr_el1;
55 
56 	__u64	spsr[KVM_NR_SPSR];
57 
58 	struct user_fpsimd_state fp_regs;
59 };
60 
61 /*
62  * Supported CPU Targets - Adding a new target type is not recommended,
63  * unless there are some special registers not supported by the
64  * genericv8 syreg table.
65  */
66 #define KVM_ARM_TARGET_AEM_V8		0
67 #define KVM_ARM_TARGET_FOUNDATION_V8	1
68 #define KVM_ARM_TARGET_CORTEX_A57	2
69 #define KVM_ARM_TARGET_XGENE_POTENZA	3
70 #define KVM_ARM_TARGET_CORTEX_A53	4
71 /* Generic ARM v8 target */
72 #define KVM_ARM_TARGET_GENERIC_V8	5
73 
74 #define KVM_ARM_NUM_TARGETS		6
75 
76 /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
77 #define KVM_ARM_DEVICE_TYPE_SHIFT	0
78 #define KVM_ARM_DEVICE_TYPE_MASK	(0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
79 #define KVM_ARM_DEVICE_ID_SHIFT		16
80 #define KVM_ARM_DEVICE_ID_MASK		(0xffff << KVM_ARM_DEVICE_ID_SHIFT)
81 
82 /* Supported device IDs */
83 #define KVM_ARM_DEVICE_VGIC_V2		0
84 
85 /* Supported VGIC address types  */
86 #define KVM_VGIC_V2_ADDR_TYPE_DIST	0
87 #define KVM_VGIC_V2_ADDR_TYPE_CPU	1
88 
89 #define KVM_VGIC_V2_DIST_SIZE		0x1000
90 #define KVM_VGIC_V2_CPU_SIZE		0x2000
91 
92 /* Supported VGICv3 address types  */
93 #define KVM_VGIC_V3_ADDR_TYPE_DIST	2
94 #define KVM_VGIC_V3_ADDR_TYPE_REDIST	3
95 #define KVM_VGIC_ITS_ADDR_TYPE		4
96 #define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION	5
97 
98 #define KVM_VGIC_V3_DIST_SIZE		SZ_64K
99 #define KVM_VGIC_V3_REDIST_SIZE		(2 * SZ_64K)
100 #define KVM_VGIC_V3_ITS_SIZE		(2 * SZ_64K)
101 
102 #define KVM_ARM_VCPU_POWER_OFF		0 /* CPU is started in OFF state */
103 #define KVM_ARM_VCPU_EL1_32BIT		1 /* CPU running a 32bit VM */
104 #define KVM_ARM_VCPU_PSCI_0_2		2 /* CPU uses PSCI v0.2 */
105 #define KVM_ARM_VCPU_PMU_V3		3 /* Support guest PMUv3 */
106 #define KVM_ARM_VCPU_SVE		4 /* enable SVE for this CPU */
107 #define KVM_ARM_VCPU_PTRAUTH_ADDRESS	5 /* VCPU uses address authentication */
108 #define KVM_ARM_VCPU_PTRAUTH_GENERIC	6 /* VCPU uses generic authentication */
109 
110 struct kvm_vcpu_init {
111 	__u32 target;
112 	__u32 features[7];
113 };
114 
115 struct kvm_sregs {
116 };
117 
118 struct kvm_fpu {
119 };
120 
121 /*
122  * See v8 ARM ARM D7.3: Debug Registers
123  *
124  * The architectural limit is 16 debug registers of each type although
125  * in practice there are usually less (see ID_AA64DFR0_EL1).
126  *
127  * Although the control registers are architecturally defined as 32
128  * bits wide we use a 64 bit structure here to keep parity with
129  * KVM_GET/SET_ONE_REG behaviour which treats all system registers as
130  * 64 bit values. It also allows for the possibility of the
131  * architecture expanding the control registers without having to
132  * change the userspace ABI.
133  */
134 #define KVM_ARM_MAX_DBG_REGS 16
135 struct kvm_guest_debug_arch {
136 	__u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS];
137 	__u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS];
138 	__u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS];
139 	__u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS];
140 };
141 
142 struct kvm_debug_exit_arch {
143 	__u32 hsr;
144 	__u64 far;	/* used for watchpoints */
145 };
146 
147 /*
148  * Architecture specific defines for kvm_guest_debug->control
149  */
150 
151 #define KVM_GUESTDBG_USE_SW_BP		(1 << 16)
152 #define KVM_GUESTDBG_USE_HW		(1 << 17)
153 
154 struct kvm_sync_regs {
155 	/* Used with KVM_CAP_ARM_USER_IRQ */
156 	__u64 device_irq_level;
157 };
158 
159 /*
160  * PMU filter structure. Describe a range of events with a particular
161  * action. To be used with KVM_ARM_VCPU_PMU_V3_FILTER.
162  */
163 struct kvm_pmu_event_filter {
164 	__u16	base_event;
165 	__u16	nevents;
166 
167 #define KVM_PMU_EVENT_ALLOW	0
168 #define KVM_PMU_EVENT_DENY	1
169 
170 	__u8	action;
171 	__u8	pad[3];
172 };
173 
174 /* for KVM_GET/SET_VCPU_EVENTS */
175 struct kvm_vcpu_events {
176 	struct {
177 		__u8 serror_pending;
178 		__u8 serror_has_esr;
179 		__u8 ext_dabt_pending;
180 		/* Align it to 8 bytes */
181 		__u8 pad[5];
182 		__u64 serror_esr;
183 	} exception;
184 	__u32 reserved[12];
185 };
186 
187 struct kvm_arm_copy_mte_tags {
188 	__u64 guest_ipa;
189 	__u64 length;
190 	void __user *addr;
191 	__u64 flags;
192 	__u64 reserved[2];
193 };
194 
195 #define KVM_ARM_TAGS_TO_GUEST		0
196 #define KVM_ARM_TAGS_FROM_GUEST		1
197 
198 /* If you need to interpret the index values, here is the key: */
199 #define KVM_REG_ARM_COPROC_MASK		0x000000000FFF0000
200 #define KVM_REG_ARM_COPROC_SHIFT	16
201 
202 /* Normal registers are mapped as coprocessor 16. */
203 #define KVM_REG_ARM_CORE		(0x0010 << KVM_REG_ARM_COPROC_SHIFT)
204 #define KVM_REG_ARM_CORE_REG(name)	(offsetof(struct kvm_regs, name) / sizeof(__u32))
205 
206 /* Some registers need more space to represent values. */
207 #define KVM_REG_ARM_DEMUX		(0x0011 << KVM_REG_ARM_COPROC_SHIFT)
208 #define KVM_REG_ARM_DEMUX_ID_MASK	0x000000000000FF00
209 #define KVM_REG_ARM_DEMUX_ID_SHIFT	8
210 #define KVM_REG_ARM_DEMUX_ID_CCSIDR	(0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
211 #define KVM_REG_ARM_DEMUX_VAL_MASK	0x00000000000000FF
212 #define KVM_REG_ARM_DEMUX_VAL_SHIFT	0
213 
214 /* AArch64 system registers */
215 #define KVM_REG_ARM64_SYSREG		(0x0013 << KVM_REG_ARM_COPROC_SHIFT)
216 #define KVM_REG_ARM64_SYSREG_OP0_MASK	0x000000000000c000
217 #define KVM_REG_ARM64_SYSREG_OP0_SHIFT	14
218 #define KVM_REG_ARM64_SYSREG_OP1_MASK	0x0000000000003800
219 #define KVM_REG_ARM64_SYSREG_OP1_SHIFT	11
220 #define KVM_REG_ARM64_SYSREG_CRN_MASK	0x0000000000000780
221 #define KVM_REG_ARM64_SYSREG_CRN_SHIFT	7
222 #define KVM_REG_ARM64_SYSREG_CRM_MASK	0x0000000000000078
223 #define KVM_REG_ARM64_SYSREG_CRM_SHIFT	3
224 #define KVM_REG_ARM64_SYSREG_OP2_MASK	0x0000000000000007
225 #define KVM_REG_ARM64_SYSREG_OP2_SHIFT	0
226 
227 #define ARM64_SYS_REG_SHIFT_MASK(x,n) \
228 	(((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \
229 	KVM_REG_ARM64_SYSREG_ ## n ## _MASK)
230 
231 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
232 	(KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \
233 	ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
234 	ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
235 	ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
236 	ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
237 	ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
238 
239 #define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64)
240 
241 /* Physical Timer EL0 Registers */
242 #define KVM_REG_ARM_PTIMER_CTL		ARM64_SYS_REG(3, 3, 14, 2, 1)
243 #define KVM_REG_ARM_PTIMER_CVAL		ARM64_SYS_REG(3, 3, 14, 2, 2)
244 #define KVM_REG_ARM_PTIMER_CNT		ARM64_SYS_REG(3, 3, 14, 0, 1)
245 
246 /*
247  * EL0 Virtual Timer Registers
248  *
249  * WARNING:
250  *      KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined
251  *      with the appropriate register encodings.  Their values have been
252  *      accidentally swapped.  As this is set API, the definitions here
253  *      must be used, rather than ones derived from the encodings.
254  */
255 #define KVM_REG_ARM_TIMER_CTL		ARM64_SYS_REG(3, 3, 14, 3, 1)
256 #define KVM_REG_ARM_TIMER_CVAL		ARM64_SYS_REG(3, 3, 14, 0, 2)
257 #define KVM_REG_ARM_TIMER_CNT		ARM64_SYS_REG(3, 3, 14, 3, 2)
258 
259 /* KVM-as-firmware specific pseudo-registers */
260 #define KVM_REG_ARM_FW			(0x0014 << KVM_REG_ARM_COPROC_SHIFT)
261 #define KVM_REG_ARM_FW_REG(r)		(KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
262 					 KVM_REG_ARM_FW | ((r) & 0xffff))
263 #define KVM_REG_ARM_PSCI_VERSION	KVM_REG_ARM_FW_REG(0)
264 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1	KVM_REG_ARM_FW_REG(1)
265 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL		0
266 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL		1
267 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED	2
268 
269 /*
270  * Only two states can be presented by the host kernel:
271  * - NOT_REQUIRED: the guest doesn't need to do anything
272  * - NOT_AVAIL: the guest isn't mitigated (it can still use SSBS if available)
273  *
274  * All the other values are deprecated. The host still accepts all
275  * values (they are ABI), but will narrow them to the above two.
276  */
277 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2	KVM_REG_ARM_FW_REG(2)
278 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL		0
279 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN		1
280 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL		2
281 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED	3
282 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED     	(1U << 4)
283 
284 /* SVE registers */
285 #define KVM_REG_ARM64_SVE		(0x15 << KVM_REG_ARM_COPROC_SHIFT)
286 
287 /* Z- and P-regs occupy blocks at the following offsets within this range: */
288 #define KVM_REG_ARM64_SVE_ZREG_BASE	0
289 #define KVM_REG_ARM64_SVE_PREG_BASE	0x400
290 #define KVM_REG_ARM64_SVE_FFR_BASE	0x600
291 
292 #define KVM_ARM64_SVE_NUM_ZREGS		__SVE_NUM_ZREGS
293 #define KVM_ARM64_SVE_NUM_PREGS		__SVE_NUM_PREGS
294 
295 #define KVM_ARM64_SVE_MAX_SLICES	32
296 
297 #define KVM_REG_ARM64_SVE_ZREG(n, i)					\
298 	(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_ZREG_BASE | \
299 	 KVM_REG_SIZE_U2048 |						\
300 	 (((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) |			\
301 	 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
302 
303 #define KVM_REG_ARM64_SVE_PREG(n, i)					\
304 	(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_PREG_BASE | \
305 	 KVM_REG_SIZE_U256 |						\
306 	 (((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) |			\
307 	 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
308 
309 #define KVM_REG_ARM64_SVE_FFR(i)					\
310 	(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_FFR_BASE | \
311 	 KVM_REG_SIZE_U256 |						\
312 	 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
313 
314 /*
315  * Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and
316  * KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness-
317  * invariant layout which differs from the layout used for the FPSIMD
318  * V-registers on big-endian systems: see sigcontext.h for more explanation.
319  */
320 
321 #define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN
322 #define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX
323 
324 /* Vector lengths pseudo-register: */
325 #define KVM_REG_ARM64_SVE_VLS		(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | \
326 					 KVM_REG_SIZE_U512 | 0xffff)
327 #define KVM_ARM64_SVE_VLS_WORDS	\
328 	((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1)
329 
330 /* Device Control API: ARM VGIC */
331 #define KVM_DEV_ARM_VGIC_GRP_ADDR	0
332 #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS	1
333 #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS	2
334 #define   KVM_DEV_ARM_VGIC_CPUID_SHIFT	32
335 #define   KVM_DEV_ARM_VGIC_CPUID_MASK	(0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
336 #define   KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
337 #define   KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
338 			(0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
339 #define   KVM_DEV_ARM_VGIC_OFFSET_SHIFT	0
340 #define   KVM_DEV_ARM_VGIC_OFFSET_MASK	(0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
341 #define   KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
342 #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS	3
343 #define KVM_DEV_ARM_VGIC_GRP_CTRL	4
344 #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
345 #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
346 #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO  7
347 #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8
348 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT	10
349 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
350 			(0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
351 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK	0x3ff
352 #define VGIC_LEVEL_INFO_LINE_LEVEL	0
353 
354 #define   KVM_DEV_ARM_VGIC_CTRL_INIT		0
355 #define   KVM_DEV_ARM_ITS_SAVE_TABLES           1
356 #define   KVM_DEV_ARM_ITS_RESTORE_TABLES        2
357 #define   KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES	3
358 #define   KVM_DEV_ARM_ITS_CTRL_RESET		4
359 
360 /* Device Control API on vcpu fd */
361 #define KVM_ARM_VCPU_PMU_V3_CTRL	0
362 #define   KVM_ARM_VCPU_PMU_V3_IRQ	0
363 #define   KVM_ARM_VCPU_PMU_V3_INIT	1
364 #define   KVM_ARM_VCPU_PMU_V3_FILTER	2
365 #define KVM_ARM_VCPU_TIMER_CTRL		1
366 #define   KVM_ARM_VCPU_TIMER_IRQ_VTIMER		0
367 #define   KVM_ARM_VCPU_TIMER_IRQ_PTIMER		1
368 #define KVM_ARM_VCPU_PVTIME_CTRL	2
369 #define   KVM_ARM_VCPU_PVTIME_IPA	0
370 
371 /* KVM_IRQ_LINE irq field index values */
372 #define KVM_ARM_IRQ_VCPU2_SHIFT		28
373 #define KVM_ARM_IRQ_VCPU2_MASK		0xf
374 #define KVM_ARM_IRQ_TYPE_SHIFT		24
375 #define KVM_ARM_IRQ_TYPE_MASK		0xf
376 #define KVM_ARM_IRQ_VCPU_SHIFT		16
377 #define KVM_ARM_IRQ_VCPU_MASK		0xff
378 #define KVM_ARM_IRQ_NUM_SHIFT		0
379 #define KVM_ARM_IRQ_NUM_MASK		0xffff
380 
381 /* irq_type field */
382 #define KVM_ARM_IRQ_TYPE_CPU		0
383 #define KVM_ARM_IRQ_TYPE_SPI		1
384 #define KVM_ARM_IRQ_TYPE_PPI		2
385 
386 /* out-of-kernel GIC cpu interrupt injection irq_number field */
387 #define KVM_ARM_IRQ_CPU_IRQ		0
388 #define KVM_ARM_IRQ_CPU_FIQ		1
389 
390 /*
391  * This used to hold the highest supported SPI, but it is now obsolete
392  * and only here to provide source code level compatibility with older
393  * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS.
394  */
395 #ifndef __KERNEL__
396 #define KVM_ARM_IRQ_GIC_MAX		127
397 #endif
398 
399 /* One single KVM irqchip, ie. the VGIC */
400 #define KVM_NR_IRQCHIPS          1
401 
402 /* PSCI interface */
403 #define KVM_PSCI_FN_BASE		0x95c1ba5e
404 #define KVM_PSCI_FN(n)			(KVM_PSCI_FN_BASE + (n))
405 
406 #define KVM_PSCI_FN_CPU_SUSPEND		KVM_PSCI_FN(0)
407 #define KVM_PSCI_FN_CPU_OFF		KVM_PSCI_FN(1)
408 #define KVM_PSCI_FN_CPU_ON		KVM_PSCI_FN(2)
409 #define KVM_PSCI_FN_MIGRATE		KVM_PSCI_FN(3)
410 
411 #define KVM_PSCI_RET_SUCCESS		PSCI_RET_SUCCESS
412 #define KVM_PSCI_RET_NI			PSCI_RET_NOT_SUPPORTED
413 #define KVM_PSCI_RET_INVAL		PSCI_RET_INVALID_PARAMS
414 #define KVM_PSCI_RET_DENIED		PSCI_RET_DENIED
415 
416 #endif
417 
418 #endif /* __ARM_KVM_H__ */
419