1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #include <hyp/switch.h>
8
9 #include <linux/arm-smccc.h>
10 #include <linux/kvm_host.h>
11 #include <linux/types.h>
12 #include <linux/jump_label.h>
13 #include <uapi/linux/psci.h>
14
15 #include <kvm/arm_psci.h>
16
17 #include <asm/barrier.h>
18 #include <asm/cpufeature.h>
19 #include <asm/kprobes.h>
20 #include <asm/kvm_asm.h>
21 #include <asm/kvm_emulate.h>
22 #include <asm/kvm_hyp.h>
23 #include <asm/kvm_mmu.h>
24 #include <asm/fpsimd.h>
25 #include <asm/debug-monitors.h>
26 #include <asm/processor.h>
27 #include <asm/thread_info.h>
28
29 /* VHE specific context */
30 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data);
31 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt);
32 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector);
33
__activate_traps(struct kvm_vcpu * vcpu)34 static void __activate_traps(struct kvm_vcpu *vcpu)
35 {
36 u64 val;
37
38 ___activate_traps(vcpu);
39
40 val = read_sysreg(cpacr_el1);
41 val |= CPACR_EL1_TTA;
42 val &= ~CPACR_EL1_ZEN;
43
44 /*
45 * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to
46 * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2,
47 * except for some missing controls, such as TAM.
48 * In this case, CPTR_EL2.TAM has the same position with or without
49 * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM
50 * shift value for trapping the AMU accesses.
51 */
52
53 val |= CPTR_EL2_TAM;
54
55 if (update_fp_enabled(vcpu)) {
56 if (vcpu_has_sve(vcpu))
57 val |= CPACR_EL1_ZEN;
58 } else {
59 val &= ~CPACR_EL1_FPEN;
60 __activate_traps_fpsimd32(vcpu);
61 }
62
63 write_sysreg(val, cpacr_el1);
64
65 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el1);
66 }
67 NOKPROBE_SYMBOL(__activate_traps);
68
__deactivate_traps(struct kvm_vcpu * vcpu)69 static void __deactivate_traps(struct kvm_vcpu *vcpu)
70 {
71 extern char vectors[]; /* kernel exception vectors */
72
73 ___deactivate_traps(vcpu);
74
75 write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
76
77 /*
78 * ARM errata 1165522 and 1530923 require the actual execution of the
79 * above before we can switch to the EL2/EL0 translation regime used by
80 * the host.
81 */
82 asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT));
83
84 write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1);
85 write_sysreg(vectors, vbar_el1);
86 }
87 NOKPROBE_SYMBOL(__deactivate_traps);
88
activate_traps_vhe_load(struct kvm_vcpu * vcpu)89 void activate_traps_vhe_load(struct kvm_vcpu *vcpu)
90 {
91 __activate_traps_common(vcpu);
92 }
93
deactivate_traps_vhe_put(struct kvm_vcpu * vcpu)94 void deactivate_traps_vhe_put(struct kvm_vcpu *vcpu)
95 {
96 __deactivate_traps_common(vcpu);
97 }
98
99 static const exit_handler_fn hyp_exit_handlers[] = {
100 [0 ... ESR_ELx_EC_MAX] = NULL,
101 [ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32,
102 [ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg,
103 [ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd,
104 [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd,
105 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low,
106 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low,
107 [ESR_ELx_EC_PAC] = kvm_hyp_handle_ptrauth,
108 };
109
kvm_get_exit_handler_array(struct kvm_vcpu * vcpu)110 static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu)
111 {
112 return hyp_exit_handlers;
113 }
114
early_exit_filter(struct kvm_vcpu * vcpu,u64 * exit_code)115 static void early_exit_filter(struct kvm_vcpu *vcpu, u64 *exit_code)
116 {
117 }
118
119 /* Switch to the guest for VHE systems running in EL2 */
__kvm_vcpu_run_vhe(struct kvm_vcpu * vcpu)120 static int __kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
121 {
122 struct kvm_cpu_context *host_ctxt;
123 struct kvm_cpu_context *guest_ctxt;
124 u64 exit_code;
125
126 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
127 host_ctxt->__hyp_running_vcpu = vcpu;
128 guest_ctxt = &vcpu->arch.ctxt;
129
130 sysreg_save_host_state_vhe(host_ctxt);
131
132 /*
133 * ARM erratum 1165522 requires us to configure both stage 1 and
134 * stage 2 translation for the guest context before we clear
135 * HCR_EL2.TGE.
136 *
137 * We have already configured the guest's stage 1 translation in
138 * kvm_vcpu_load_sysregs_vhe above. We must now call
139 * __load_stage2 before __activate_traps, because
140 * __load_stage2 configures stage 2 translation, and
141 * __activate_traps clear HCR_EL2.TGE (among other things).
142 */
143 __load_stage2(vcpu->arch.hw_mmu, vcpu->arch.hw_mmu->arch);
144 __activate_traps(vcpu);
145
146 __kvm_adjust_pc(vcpu);
147
148 sysreg_restore_guest_state_vhe(guest_ctxt);
149 __debug_switch_to_guest(vcpu);
150
151 do {
152 /* Jump in the fire! */
153 exit_code = __guest_enter(vcpu);
154
155 /* And we're baaack! */
156 } while (fixup_guest_exit(vcpu, &exit_code));
157
158 sysreg_save_guest_state_vhe(guest_ctxt);
159
160 __deactivate_traps(vcpu);
161
162 sysreg_restore_host_state_vhe(host_ctxt);
163
164 if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED)
165 __fpsimd_save_fpexc32(vcpu);
166
167 __debug_switch_to_host(vcpu);
168
169 return exit_code;
170 }
171 NOKPROBE_SYMBOL(__kvm_vcpu_run_vhe);
172
__kvm_vcpu_run(struct kvm_vcpu * vcpu)173 int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
174 {
175 int ret;
176
177 local_daif_mask();
178
179 /*
180 * Having IRQs masked via PMR when entering the guest means the GIC
181 * will not signal the CPU of interrupts of lower priority, and the
182 * only way to get out will be via guest exceptions.
183 * Naturally, we want to avoid this.
184 *
185 * local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a
186 * dsb to ensure the redistributor is forwards EL2 IRQs to the CPU.
187 */
188 pmr_sync();
189
190 ret = __kvm_vcpu_run_vhe(vcpu);
191
192 /*
193 * local_daif_restore() takes care to properly restore PSTATE.DAIF
194 * and the GIC PMR if the host is using IRQ priorities.
195 */
196 local_daif_restore(DAIF_PROCCTX_NOIRQ);
197
198 /*
199 * When we exit from the guest we change a number of CPU configuration
200 * parameters, such as traps. Make sure these changes take effect
201 * before running the host or additional guests.
202 */
203 isb();
204
205 return ret;
206 }
207
__hyp_call_panic(u64 spsr,u64 elr,u64 par)208 static void __hyp_call_panic(u64 spsr, u64 elr, u64 par)
209 {
210 struct kvm_cpu_context *host_ctxt;
211 struct kvm_vcpu *vcpu;
212
213 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
214 vcpu = host_ctxt->__hyp_running_vcpu;
215
216 __deactivate_traps(vcpu);
217 sysreg_restore_host_state_vhe(host_ctxt);
218
219 panic("HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n",
220 spsr, elr,
221 read_sysreg_el2(SYS_ESR), read_sysreg_el2(SYS_FAR),
222 read_sysreg(hpfar_el2), par, vcpu);
223 }
224 NOKPROBE_SYMBOL(__hyp_call_panic);
225
hyp_panic(void)226 void __noreturn hyp_panic(void)
227 {
228 u64 spsr = read_sysreg_el2(SYS_SPSR);
229 u64 elr = read_sysreg_el2(SYS_ELR);
230 u64 par = read_sysreg_par();
231
232 __hyp_call_panic(spsr, elr, par);
233 unreachable();
234 }
235
kvm_unexpected_el2_exception(void)236 asmlinkage void kvm_unexpected_el2_exception(void)
237 {
238 return __kvm_unexpected_el2_exception();
239 }
240