1 /*
2  * Copyright 2000, 2007-2008 MontaVista Software Inc.
3  * Author: MontaVista Software, Inc. <source@mvista.com
4  *
5  * Updates to 2.6, Pete Popov, Embedded Alley Solutions, Inc.
6  *
7  *  This program is free software; you can redistribute  it and/or modify it
8  *  under  the terms of  the GNU General  Public License as published by the
9  *  Free Software Foundation;  either version 2 of the  License, or (at your
10  *  option) any later version.
11  *
12  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
13  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
14  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
15  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
16  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
18  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
20  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22  *
23  *  You should have received a copy of the  GNU General Public License along
24  *  with this program; if not, write  to the Free Software Foundation, Inc.,
25  *  675 Mass Ave, Cambridge, MA 02139, USA.
26  */
27 
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/mm.h>
31 #include <linux/dma-map-ops.h> /* for dma_default_coherent */
32 
33 #include <asm/mipsregs.h>
34 
35 #include <au1000.h>
36 
37 extern void __init board_setup(void);
38 extern void __init alchemy_set_lpj(void);
39 
alchemy_dma_coherent(void)40 static bool alchemy_dma_coherent(void)
41 {
42 	switch (alchemy_get_cputype()) {
43 	case ALCHEMY_CPU_AU1000:
44 	case ALCHEMY_CPU_AU1500:
45 	case ALCHEMY_CPU_AU1100:
46 		return false;
47 	case ALCHEMY_CPU_AU1200:
48 		/* Au1200 AB USB does not support coherent memory */
49 		if ((read_c0_prid() & PRID_REV_MASK) == 0)
50 			return false;
51 		return true;
52 	default:
53 		return true;
54 	}
55 }
56 
plat_mem_setup(void)57 void __init plat_mem_setup(void)
58 {
59 	alchemy_set_lpj();
60 
61 	if (au1xxx_cpu_needs_config_od())
62 		/* Various early Au1xx0 errata corrected by this */
63 		set_c0_config(1 << 19); /* Set Config[OD] */
64 	else
65 		/* Clear to obtain best system bus performance */
66 		clear_c0_config(1 << 19); /* Clear Config[OD] */
67 
68 	dma_default_coherent = alchemy_dma_coherent();
69 
70 	board_setup();	/* board specific setup */
71 
72 	/* IO/MEM resources. */
73 	set_io_port_base(0);
74 	ioport_resource.start = IOPORT_RESOURCE_START;
75 	ioport_resource.end = IOPORT_RESOURCE_END;
76 	iomem_resource.start = IOMEM_RESOURCE_START;
77 	iomem_resource.end = IOMEM_RESOURCE_END;
78 }
79 
80 #ifdef CONFIG_MIPS_FIXUP_BIGPHYS_ADDR
81 /* This routine should be valid for all Au1x based boards */
fixup_bigphys_addr(phys_addr_t phys_addr,phys_addr_t size)82 phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
83 {
84 	unsigned long start = ALCHEMY_PCI_MEMWIN_START;
85 	unsigned long end = ALCHEMY_PCI_MEMWIN_END;
86 
87 	/* Don't fixup 36-bit addresses */
88 	if ((phys_addr >> 32) != 0)
89 		return phys_addr;
90 
91 	/* Check for PCI memory window */
92 	if (phys_addr >= start && (phys_addr + size - 1) <= end)
93 		return (phys_addr_t)(AU1500_PCI_MEM_PHYS_ADDR + phys_addr);
94 
95 	/* default nop */
96 	return phys_addr;
97 }
98 
io_remap_pfn_range(struct vm_area_struct * vma,unsigned long vaddr,unsigned long pfn,unsigned long size,pgprot_t prot)99 int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long vaddr,
100 		unsigned long pfn, unsigned long size, pgprot_t prot)
101 {
102 	phys_addr_t phys_addr = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
103 
104 	return remap_pfn_range(vma, vaddr, phys_addr >> PAGE_SHIFT, size, prot);
105 }
106 EXPORT_SYMBOL(io_remap_pfn_range);
107 #endif /* CONFIG_MIPS_FIXUP_BIGPHYS_ADDR */
108