1// SPDX-License-Identifier: GPL-2.0
2/ {
3	#address-cells = <1>;
4	#size-cells = <1>;
5	compatible = "brcm,bcm7346";
6
7	cpus {
8		#address-cells = <1>;
9		#size-cells = <0>;
10
11		mips-hpt-frequency = <163125000>;
12
13		cpu@0 {
14			compatible = "brcm,bmips5000";
15			device_type = "cpu";
16			reg = <0>;
17		};
18
19		cpu@1 {
20			compatible = "brcm,bmips5000";
21			device_type = "cpu";
22			reg = <1>;
23		};
24	};
25
26	aliases {
27		uart0 = &uart0;
28	};
29
30	cpu_intc: interrupt-controller {
31		#address-cells = <0>;
32		compatible = "mti,cpu-interrupt-controller";
33
34		interrupt-controller;
35		#interrupt-cells = <1>;
36	};
37
38	clocks {
39		uart_clk: uart_clk {
40			compatible = "fixed-clock";
41			#clock-cells = <0>;
42			clock-frequency = <81000000>;
43		};
44
45		upg_clk: upg_clk {
46			compatible = "fixed-clock";
47			#clock-cells = <0>;
48			clock-frequency = <27000000>;
49		};
50	};
51
52	rdb {
53		#address-cells = <1>;
54		#size-cells = <1>;
55
56		compatible = "simple-bus";
57		ranges = <0 0x10000000 0x01000000>;
58
59		periph_intc: interrupt-controller@411400 {
60			compatible = "brcm,bcm7038-l1-intc";
61			reg = <0x411400 0x30>, <0x411600 0x30>;
62
63			interrupt-controller;
64			#interrupt-cells = <1>;
65
66			interrupt-parent = <&cpu_intc>;
67			interrupts = <2>, <3>;
68		};
69
70		sun_l2_intc: interrupt-controller@403000 {
71			compatible = "brcm,l2-intc";
72			reg = <0x403000 0x30>;
73			interrupt-controller;
74			#interrupt-cells = <1>;
75			interrupt-parent = <&periph_intc>;
76			interrupts = <51>;
77		};
78
79		gisb-arb@400000 {
80			compatible = "brcm,bcm7400-gisb-arb";
81			reg = <0x400000 0xdc>;
82			native-endian;
83			interrupt-parent = <&sun_l2_intc>;
84			interrupts = <0>, <2>;
85			brcm,gisb-arb-master-mask = <0x673>;
86			brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
87						     "rdc_0", "raaga_0",
88						     "jtag_0", "svd_0";
89		};
90
91		upg_irq0_intc: interrupt-controller@406780 {
92			compatible = "brcm,bcm7120-l2-intc";
93			reg = <0x406780 0x8>;
94
95			brcm,int-map-mask = <0x44>, <0xf000000>;
96			brcm,int-fwd-mask = <0x70000>;
97
98			interrupt-controller;
99			#interrupt-cells = <1>;
100
101			interrupt-parent = <&periph_intc>;
102			interrupts = <59>, <57>;
103			interrupt-names = "upg_main", "upg_bsc";
104		};
105
106		upg_aon_irq0_intc: interrupt-controller@408b80 {
107			compatible = "brcm,bcm7120-l2-intc";
108			reg = <0x408b80 0x8>;
109
110			brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
111			brcm,int-fwd-mask = <0>;
112			brcm,irq-can-wake;
113
114			interrupt-controller;
115			#interrupt-cells = <1>;
116
117			interrupt-parent = <&periph_intc>;
118			interrupts = <60>, <58>, <62>;
119			interrupt-names = "upg_main_aon", "upg_bsc_aon",
120					  "upg_spi";
121		};
122
123		sun_top_ctrl: syscon@404000 {
124			compatible = "brcm,bcm7346-sun-top-ctrl", "syscon";
125			reg = <0x404000 0x51c>;
126			native-endian;
127		};
128
129		reboot {
130			compatible = "brcm,brcmstb-reboot";
131			syscon = <&sun_top_ctrl 0x304 0x308>;
132		};
133
134		uart0: serial@406900 {
135			compatible = "ns16550a";
136			reg = <0x406900 0x20>;
137			reg-io-width = <0x4>;
138			reg-shift = <0x2>;
139			native-endian;
140			interrupt-parent = <&periph_intc>;
141			interrupts = <64>;
142			clocks = <&uart_clk>;
143			status = "disabled";
144		};
145
146		uart1: serial@406940 {
147			compatible = "ns16550a";
148			reg = <0x406940 0x20>;
149			reg-io-width = <0x4>;
150			reg-shift = <0x2>;
151			native-endian;
152			interrupt-parent = <&periph_intc>;
153			interrupts = <65>;
154			clocks = <&uart_clk>;
155			status = "disabled";
156		};
157
158		uart2: serial@406980 {
159			compatible = "ns16550a";
160			reg = <0x406980 0x20>;
161			reg-io-width = <0x4>;
162			reg-shift = <0x2>;
163			native-endian;
164			interrupt-parent = <&periph_intc>;
165			interrupts = <66>;
166			clocks = <&uart_clk>;
167			status = "disabled";
168		};
169
170		bsca: i2c@406200 {
171		      clock-frequency = <390000>;
172		      compatible = "brcm,brcmstb-i2c";
173		      interrupt-parent = <&upg_irq0_intc>;
174		      reg = <0x406200 0x58>;
175		      interrupts = <24>;
176		      interrupt-names = "upg_bsca";
177		      status = "disabled";
178		};
179
180		bscb: i2c@406280 {
181		      clock-frequency = <390000>;
182		      compatible = "brcm,brcmstb-i2c";
183		      interrupt-parent = <&upg_irq0_intc>;
184		      reg = <0x406280 0x58>;
185		      interrupts = <25>;
186		      interrupt-names = "upg_bscb";
187		      status = "disabled";
188		};
189
190		bscc: i2c@406300 {
191		      clock-frequency = <390000>;
192		      compatible = "brcm,brcmstb-i2c";
193		      interrupt-parent = <&upg_irq0_intc>;
194		      reg = <0x406300 0x58>;
195		      interrupts = <26>;
196		      interrupt-names = "upg_bscc";
197		      status = "disabled";
198		};
199
200		bscd: i2c@406380 {
201		      clock-frequency = <390000>;
202		      compatible = "brcm,brcmstb-i2c";
203		      interrupt-parent = <&upg_irq0_intc>;
204		      reg = <0x406380 0x58>;
205		      interrupts = <27>;
206		      interrupt-names = "upg_bscd";
207		      status = "disabled";
208		};
209
210		bsce: i2c@408980 {
211		      clock-frequency = <390000>;
212		      compatible = "brcm,brcmstb-i2c";
213		      interrupt-parent = <&upg_aon_irq0_intc>;
214		      reg = <0x408980 0x58>;
215		      interrupts = <27>;
216		      interrupt-names = "upg_bsce";
217		      status = "disabled";
218		};
219
220		pwma: pwm@406580 {
221			compatible = "brcm,bcm7038-pwm";
222			reg = <0x406580 0x28>;
223			#pwm-cells = <2>;
224			clocks = <&upg_clk>;
225			status = "disabled";
226		};
227
228		pwmb: pwm@406800 {
229			compatible = "brcm,bcm7038-pwm";
230			reg = <0x406800 0x28>;
231			#pwm-cells = <2>;
232			clocks = <&upg_clk>;
233			status = "disabled";
234		};
235
236		watchdog: watchdog@4067e8 {
237			clocks = <&upg_clk>;
238			compatible = "brcm,bcm7038-wdt";
239			reg = <0x4067e8 0x14>;
240			status = "disabled";
241		};
242
243		aon_pm_l2_intc: interrupt-controller@408440 {
244			compatible = "brcm,l2-intc";
245			reg = <0x408440 0x30>;
246			interrupt-controller;
247			#interrupt-cells = <1>;
248			interrupt-parent = <&periph_intc>;
249			interrupts = <53>;
250			brcm,irq-can-wake;
251		};
252
253		aon_ctrl: syscon@408000 {
254			compatible = "brcm,brcmstb-aon-ctrl";
255			reg = <0x408000 0x100>, <0x408200 0x200>;
256			reg-names = "aon-ctrl", "aon-sram";
257		};
258
259		timers: timer@4067c0 {
260			compatible = "brcm,brcmstb-timers";
261			reg = <0x4067c0 0x40>;
262		};
263
264		upg_gio: gpio@406700 {
265			compatible = "brcm,brcmstb-gpio";
266			reg = <0x406700 0x60>;
267			#gpio-cells = <2>;
268			#interrupt-cells = <2>;
269			gpio-controller;
270			interrupt-controller;
271			interrupt-parent = <&upg_irq0_intc>;
272			interrupts = <6>;
273			brcm,gpio-bank-widths = <32 32 16>;
274		};
275
276		upg_gio_aon: gpio@408c00 {
277			compatible = "brcm,brcmstb-gpio";
278			reg = <0x408c00 0x60>;
279			#gpio-cells = <2>;
280			#interrupt-cells = <2>;
281			gpio-controller;
282			interrupt-controller;
283			interrupt-parent = <&upg_aon_irq0_intc>;
284			interrupts = <6>;
285			interrupts-extended = <&upg_aon_irq0_intc 6>,
286					      <&aon_pm_l2_intc 5>;
287			wakeup-source;
288			brcm,gpio-bank-widths = <27 32 2>;
289		};
290
291		enet0: ethernet@430000 {
292			phy-mode = "internal";
293			phy-handle = <&phy1>;
294			mac-address = [ 00 10 18 36 23 1a ];
295			compatible = "brcm,genet-v2";
296			#address-cells = <0x1>;
297			#size-cells = <0x1>;
298			reg = <0x430000 0x4c8c>;
299			interrupts = <24>, <25>;
300			interrupt-parent = <&periph_intc>;
301			status = "disabled";
302
303			mdio@e14 {
304				compatible = "brcm,genet-mdio-v2";
305				#address-cells = <0x1>;
306				#size-cells = <0x0>;
307				reg = <0xe14 0x8>;
308
309				phy1: ethernet-phy@1 {
310					max-speed = <100>;
311					reg = <0x1>;
312					compatible = "brcm,40nm-ephy",
313						"ethernet-phy-ieee802.3-c22";
314				};
315			};
316		};
317
318		ehci0: usb@480300 {
319			compatible = "brcm,bcm7346-ehci", "generic-ehci";
320			reg = <0x480300 0x100>;
321			native-endian;
322			interrupt-parent = <&periph_intc>;
323			interrupts = <68>;
324			status = "disabled";
325		};
326
327		ohci0: usb@480400 {
328			compatible = "brcm,bcm7346-ohci", "generic-ohci";
329			reg = <0x480400 0x100>;
330			native-endian;
331			no-big-frame-no;
332			interrupt-parent = <&periph_intc>;
333			interrupts = <70>;
334			status = "disabled";
335		};
336
337		ehci1: usb@480500 {
338			compatible = "brcm,bcm7346-ehci", "generic-ehci";
339			reg = <0x480500 0x100>;
340			native-endian;
341			interrupt-parent = <&periph_intc>;
342			interrupts = <69>;
343			status = "disabled";
344		};
345
346		ohci1: usb@480600 {
347			compatible = "brcm,bcm7346-ohci", "generic-ohci";
348			reg = <0x480600 0x100>;
349			native-endian;
350			no-big-frame-no;
351			interrupt-parent = <&periph_intc>;
352			interrupts = <71>;
353			status = "disabled";
354		};
355
356		ehci2: usb@490300 {
357			compatible = "brcm,bcm7346-ehci", "generic-ehci";
358			reg = <0x490300 0x100>;
359			native-endian;
360			interrupt-parent = <&periph_intc>;
361			interrupts = <73>;
362			status = "disabled";
363		};
364
365		ohci2: usb@490400 {
366			compatible = "brcm,bcm7346-ohci", "generic-ohci";
367			reg = <0x490400 0x100>;
368			native-endian;
369			no-big-frame-no;
370			interrupt-parent = <&periph_intc>;
371			interrupts = <75>;
372			status = "disabled";
373		};
374
375		ehci3: usb@490500 {
376			compatible = "brcm,bcm7346-ehci", "generic-ehci";
377			reg = <0x490500 0x100>;
378			native-endian;
379			interrupt-parent = <&periph_intc>;
380			interrupts = <74>;
381			status = "disabled";
382		};
383
384		ohci3: usb@490600 {
385			compatible = "brcm,bcm7346-ohci", "generic-ohci";
386			reg = <0x490600 0x100>;
387			native-endian;
388			no-big-frame-no;
389			interrupt-parent = <&periph_intc>;
390			interrupts = <76>;
391			status = "disabled";
392		};
393
394		hif_l2_intc: interrupt-controller@411000 {
395			compatible = "brcm,l2-intc";
396			reg = <0x411000 0x30>;
397			interrupt-controller;
398			#interrupt-cells = <1>;
399			interrupt-parent = <&periph_intc>;
400			interrupts = <30>;
401		};
402
403		nand: nand@412800 {
404			compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
405			#address-cells = <1>;
406			#size-cells = <0>;
407			reg-names = "nand";
408			reg = <0x412800 0x400>;
409			interrupt-parent = <&hif_l2_intc>;
410			interrupts = <24>;
411			status = "disabled";
412		};
413
414		sata: sata@181000 {
415			compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
416			reg-names = "ahci", "top-ctrl";
417			reg = <0x181000 0xa9c>, <0x180020 0x1c>;
418			interrupt-parent = <&periph_intc>;
419			interrupts = <40>;
420			#address-cells = <1>;
421			#size-cells = <0>;
422			status = "disabled";
423
424			sata0: sata-port@0 {
425				reg = <0>;
426				phys = <&sata_phy0>;
427			};
428
429			sata1: sata-port@1 {
430				reg = <1>;
431				phys = <&sata_phy1>;
432			};
433		};
434
435		sata_phy: sata-phy@180100 {
436			compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
437			reg = <0x180100 0x0eff>;
438			reg-names = "phy";
439			#address-cells = <1>;
440			#size-cells = <0>;
441			status = "disabled";
442
443			sata_phy0: sata-phy@0 {
444				reg = <0>;
445				#phy-cells = <0>;
446			};
447
448			sata_phy1: sata-phy@1 {
449				reg = <1>;
450				#phy-cells = <0>;
451			};
452		};
453
454		sdhci0: sdhci@413500 {
455			compatible = "brcm,bcm7425-sdhci";
456			reg = <0x413500 0x100>;
457			interrupt-parent = <&periph_intc>;
458			interrupts = <85>;
459			status = "disabled";
460		};
461
462		spi_l2_intc: interrupt-controller@411d00 {
463			compatible = "brcm,l2-intc";
464			reg = <0x411d00 0x30>;
465			interrupt-controller;
466			#interrupt-cells = <1>;
467			interrupt-parent = <&periph_intc>;
468			interrupts = <31>;
469		};
470
471		qspi: spi@413000 {
472			#address-cells = <0x1>;
473			#size-cells = <0x0>;
474			compatible = "brcm,spi-bcm-qspi",
475				     "brcm,spi-brcmstb-qspi";
476			clocks = <&upg_clk>;
477			reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
478			reg-names = "cs_reg", "hif_mspi", "bspi";
479			interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
480			interrupt-parent = <&spi_l2_intc>;
481			interrupt-names = "spi_lr_fullness_reached",
482					  "spi_lr_session_aborted",
483					  "spi_lr_impatient",
484					  "spi_lr_session_done",
485					  "spi_lr_overread",
486					  "mspi_done",
487					  "mspi_halted";
488			status = "disabled";
489		};
490
491		mspi: spi@408a00 {
492			#address-cells = <1>;
493			#size-cells = <0>;
494			compatible = "brcm,spi-bcm-qspi",
495				     "brcm,spi-brcmstb-mspi";
496			clocks = <&upg_clk>;
497			reg = <0x408a00 0x180>;
498			reg-names = "mspi";
499			interrupts = <0x14>;
500			interrupt-parent = <&upg_aon_irq0_intc>;
501			interrupt-names = "mspi_done";
502			status = "disabled";
503		};
504
505		waketimer: waketimer@408e80 {
506			compatible = "brcm,brcmstb-waketimer";
507			reg = <0x408e80 0x14>;
508			interrupts = <0x3>;
509			interrupt-parent = <&aon_pm_l2_intc>;
510			interrupt-names = "timer";
511			clocks = <&upg_clk>;
512			status = "disabled";
513		};
514	};
515
516	memory_controllers {
517		compatible = "simple-bus";
518		ranges = <0x0 0x103b0000 0xa000>;
519		#address-cells = <1>;
520		#size-cells = <1>;
521
522		memory-controller@0 {
523			compatible = "brcm,brcmstb-memc", "simple-bus";
524			ranges = <0x0 0x0 0xa000>;
525			#address-cells = <1>;
526			#size-cells = <1>;
527
528			memc-arb@1000 {
529				compatible = "brcm,brcmstb-memc-arb";
530				reg = <0x1000 0x248>;
531			};
532
533			memc-ddr@2000 {
534				compatible = "brcm,brcmstb-memc-ddr";
535				reg = <0x2000 0x300>;
536			};
537
538			ddr-phy@6000 {
539				compatible = "brcm,brcmstb-ddr-phy";
540				reg = <0x6000 0xc8>;
541			};
542
543			shimphy@8000 {
544				compatible = "brcm,brcmstb-ddr-shimphy";
545				reg = <0x8000 0x13c>;
546			};
547		};
548	};
549};
550