1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
4  *
5  * Loongson 1 Clock Register Definitions.
6  */
7 
8 #ifndef __ASM_MACH_LOONGSON32_REGS_CLK_H
9 #define __ASM_MACH_LOONGSON32_REGS_CLK_H
10 
11 #define LS1X_CLK_REG(x) \
12 		((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x)))
13 
14 #define LS1X_CLK_PLL_FREQ		LS1X_CLK_REG(0x0)
15 #define LS1X_CLK_PLL_DIV		LS1X_CLK_REG(0x4)
16 
17 #if defined(CONFIG_LOONGSON1_LS1B)
18 /* Clock PLL Divisor Register Bits */
19 #define DIV_DC_EN			BIT(31)
20 #define DIV_DC_RST			BIT(30)
21 #define DIV_CPU_EN			BIT(25)
22 #define DIV_CPU_RST			BIT(24)
23 #define DIV_DDR_EN			BIT(19)
24 #define DIV_DDR_RST			BIT(18)
25 #define RST_DC_EN			BIT(5)
26 #define RST_DC				BIT(4)
27 #define RST_DDR_EN			BIT(3)
28 #define RST_DDR				BIT(2)
29 #define RST_CPU_EN			BIT(1)
30 #define RST_CPU				BIT(0)
31 
32 #define DIV_DC_SHIFT			26
33 #define DIV_CPU_SHIFT			20
34 #define DIV_DDR_SHIFT			14
35 
36 #define DIV_DC_WIDTH			4
37 #define DIV_CPU_WIDTH			4
38 #define DIV_DDR_WIDTH			4
39 
40 #define BYPASS_DC_SHIFT			12
41 #define BYPASS_DDR_SHIFT		10
42 #define BYPASS_CPU_SHIFT		8
43 
44 #define BYPASS_DC_WIDTH			1
45 #define BYPASS_DDR_WIDTH		1
46 #define BYPASS_CPU_WIDTH		1
47 
48 #elif defined(CONFIG_LOONGSON1_LS1C)
49 /* PLL/SDRAM Frequency configuration register Bits */
50 #define PLL_VALID			BIT(31)
51 #define FRAC_N				GENMASK(23, 16)
52 #define RST_TIME			GENMASK(3, 2)
53 #define SDRAM_DIV			GENMASK(1, 0)
54 
55 /* CPU/CAMERA/DC Frequency configuration register Bits */
56 #define DIV_DC_EN			BIT(31)
57 #define DIV_DC				GENMASK(30, 24)
58 #define DIV_CAM_EN			BIT(23)
59 #define DIV_CAM				GENMASK(22, 16)
60 #define DIV_CPU_EN			BIT(15)
61 #define DIV_CPU				GENMASK(14, 8)
62 #define DIV_DC_SEL_EN			BIT(5)
63 #define DIV_DC_SEL			BIT(4)
64 #define DIV_CAM_SEL_EN			BIT(3)
65 #define DIV_CAM_SEL			BIT(2)
66 #define DIV_CPU_SEL_EN			BIT(1)
67 #define DIV_CPU_SEL			BIT(0)
68 
69 #define DIV_DC_SHIFT			24
70 #define DIV_CAM_SHIFT			16
71 #define DIV_CPU_SHIFT			8
72 #define DIV_DDR_SHIFT			0
73 
74 #define DIV_DC_WIDTH			7
75 #define DIV_CAM_WIDTH			7
76 #define DIV_CPU_WIDTH			7
77 #define DIV_DDR_WIDTH			2
78 
79 #endif
80 
81 #endif /* __ASM_MACH_LOONGSON32_REGS_CLK_H */
82