1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * 4 * Parts of this file are based on Ralink's 2.6.21 BSP 5 * 6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 8 * Copyright (C) 2013 John Crispin <john@phrozen.org> 9 */ 10 11 #ifndef _RT305X_REGS_H_ 12 #define _RT305X_REGS_H_ 13 14 extern enum ralink_soc_type ralink_soc; 15 soc_is_rt3050(void)16static inline int soc_is_rt3050(void) 17 { 18 return ralink_soc == RT305X_SOC_RT3050; 19 } 20 soc_is_rt3052(void)21static inline int soc_is_rt3052(void) 22 { 23 return ralink_soc == RT305X_SOC_RT3052; 24 } 25 soc_is_rt305x(void)26static inline int soc_is_rt305x(void) 27 { 28 return soc_is_rt3050() || soc_is_rt3052(); 29 } 30 soc_is_rt3350(void)31static inline int soc_is_rt3350(void) 32 { 33 return ralink_soc == RT305X_SOC_RT3350; 34 } 35 soc_is_rt3352(void)36static inline int soc_is_rt3352(void) 37 { 38 return ralink_soc == RT305X_SOC_RT3352; 39 } 40 soc_is_rt5350(void)41static inline int soc_is_rt5350(void) 42 { 43 return ralink_soc == RT305X_SOC_RT5350; 44 } 45 46 #define RT305X_SYSC_BASE 0x10000000 47 48 #define SYSC_REG_CHIP_NAME0 0x00 49 #define SYSC_REG_CHIP_NAME1 0x04 50 #define SYSC_REG_CHIP_ID 0x0c 51 #define SYSC_REG_SYSTEM_CONFIG 0x10 52 53 #define RT3052_CHIP_NAME0 0x30335452 54 #define RT3052_CHIP_NAME1 0x20203235 55 56 #define RT3350_CHIP_NAME0 0x33335452 57 #define RT3350_CHIP_NAME1 0x20203035 58 59 #define RT3352_CHIP_NAME0 0x33335452 60 #define RT3352_CHIP_NAME1 0x20203235 61 62 #define RT5350_CHIP_NAME0 0x33355452 63 #define RT5350_CHIP_NAME1 0x20203035 64 65 #define CHIP_ID_ID_MASK 0xff 66 #define CHIP_ID_ID_SHIFT 8 67 #define CHIP_ID_REV_MASK 0xff 68 69 #define RT305X_SYSCFG_CPUCLK_SHIFT 18 70 #define RT305X_SYSCFG_CPUCLK_MASK 0x1 71 #define RT305X_SYSCFG_CPUCLK_LOW 0x0 72 #define RT305X_SYSCFG_CPUCLK_HIGH 0x1 73 74 #define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2 75 #define RT305X_SYSCFG_CPUCLK_MASK 0x1 76 #define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 0x1 77 78 #define RT3352_SYSCFG0_CPUCLK_SHIFT 8 79 #define RT3352_SYSCFG0_CPUCLK_MASK 0x1 80 #define RT3352_SYSCFG0_CPUCLK_LOW 0x0 81 #define RT3352_SYSCFG0_CPUCLK_HIGH 0x1 82 83 #define RT5350_SYSCFG0_CPUCLK_SHIFT 8 84 #define RT5350_SYSCFG0_CPUCLK_MASK 0x3 85 #define RT5350_SYSCFG0_CPUCLK_360 0x0 86 #define RT5350_SYSCFG0_CPUCLK_320 0x2 87 #define RT5350_SYSCFG0_CPUCLK_300 0x3 88 89 #define RT5350_SYSCFG0_DRAM_SIZE_SHIFT 12 90 #define RT5350_SYSCFG0_DRAM_SIZE_MASK 7 91 #define RT5350_SYSCFG0_DRAM_SIZE_2M 0 92 #define RT5350_SYSCFG0_DRAM_SIZE_8M 1 93 #define RT5350_SYSCFG0_DRAM_SIZE_16M 2 94 #define RT5350_SYSCFG0_DRAM_SIZE_32M 3 95 #define RT5350_SYSCFG0_DRAM_SIZE_64M 4 96 97 /* multi function gpio pins */ 98 #define RT305X_GPIO_I2C_SD 1 99 #define RT305X_GPIO_I2C_SCLK 2 100 #define RT305X_GPIO_SPI_EN 3 101 #define RT305X_GPIO_SPI_CLK 4 102 /* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */ 103 #define RT305X_GPIO_7 7 104 #define RT305X_GPIO_10 10 105 #define RT305X_GPIO_14 14 106 #define RT305X_GPIO_UART1_TXD 15 107 #define RT305X_GPIO_UART1_RXD 16 108 #define RT305X_GPIO_JTAG_TDO 17 109 #define RT305X_GPIO_JTAG_TDI 18 110 #define RT305X_GPIO_MDIO_MDC 22 111 #define RT305X_GPIO_MDIO_MDIO 23 112 #define RT305X_GPIO_SDRAM_MD16 24 113 #define RT305X_GPIO_SDRAM_MD31 39 114 #define RT305X_GPIO_GE0_TXD0 40 115 #define RT305X_GPIO_GE0_RXCLK 51 116 117 #define RT3352_SYSC_REG_SYSCFG0 0x010 118 #define RT3352_SYSC_REG_SYSCFG1 0x014 119 #define RT3352_SYSC_REG_CLKCFG1 0x030 120 #define RT3352_SYSC_REG_RSTCTRL 0x034 121 #define RT3352_SYSC_REG_USB_PS 0x05c 122 123 #define RT3352_CLKCFG0_XTAL_SEL BIT(20) 124 #define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18) 125 #define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20) 126 #define RT3352_RSTCTRL_UHST BIT(22) 127 #define RT3352_RSTCTRL_UDEV BIT(25) 128 #define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10) 129 130 #define RT305X_SDRAM_BASE 0x00000000 131 #define RT305X_MEM_SIZE_MIN 2 132 #define RT305X_MEM_SIZE_MAX 64 133 #define RT3352_MEM_SIZE_MIN 2 134 #define RT3352_MEM_SIZE_MAX 256 135 136 #endif 137