1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (C) 2000,2001,2004 Broadcom Corporation
4  */
5 #include <linux/clockchips.h>
6 #include <linux/interrupt.h>
7 #include <linux/percpu.h>
8 #include <linux/smp.h>
9 #include <linux/irq.h>
10 
11 #include <asm/addrspace.h>
12 #include <asm/io.h>
13 #include <asm/time.h>
14 
15 #include <asm/sibyte/bcm1480_regs.h>
16 #include <asm/sibyte/sb1250_regs.h>
17 #include <asm/sibyte/bcm1480_int.h>
18 #include <asm/sibyte/bcm1480_scd.h>
19 
20 #include <asm/sibyte/sb1250.h>
21 
22 #define IMR_IP2_VAL	K_BCM1480_INT_MAP_I0
23 #define IMR_IP3_VAL	K_BCM1480_INT_MAP_I1
24 #define IMR_IP4_VAL	K_BCM1480_INT_MAP_I2
25 
26 /*
27  * The general purpose timer ticks at 1MHz independent if
28  * the rest of the system
29  */
30 
sibyte_set_periodic(struct clock_event_device * evt)31 static int sibyte_set_periodic(struct clock_event_device *evt)
32 {
33 	unsigned int cpu = smp_processor_id();
34 	void __iomem *cfg, *init;
35 
36 	cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
37 	init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
38 
39 	__raw_writeq(0, cfg);
40 	__raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init);
41 	__raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg);
42 	return 0;
43 }
44 
sibyte_shutdown(struct clock_event_device * evt)45 static int sibyte_shutdown(struct clock_event_device *evt)
46 {
47 	unsigned int cpu = smp_processor_id();
48 	void __iomem *cfg;
49 
50 	cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
51 
52 	/* Stop the timer until we actually program a shot */
53 	__raw_writeq(0, cfg);
54 	return 0;
55 }
56 
sibyte_next_event(unsigned long delta,struct clock_event_device * cd)57 static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd)
58 {
59 	unsigned int cpu = smp_processor_id();
60 	void __iomem *cfg, *init;
61 
62 	cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
63 	init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
64 
65 	__raw_writeq(0, cfg);
66 	__raw_writeq(delta - 1, init);
67 	__raw_writeq(M_SCD_TIMER_ENABLE, cfg);
68 
69 	return 0;
70 }
71 
sibyte_counter_handler(int irq,void * dev_id)72 static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
73 {
74 	unsigned int cpu = smp_processor_id();
75 	struct clock_event_device *cd = dev_id;
76 	void __iomem *cfg;
77 	unsigned long tmode;
78 
79 	if (clockevent_state_periodic(cd))
80 		tmode = M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS;
81 	else
82 		tmode = 0;
83 
84 	/* ACK interrupt */
85 	cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
86 	____raw_writeq(tmode, cfg);
87 
88 	cd->event_handler(cd);
89 
90 	return IRQ_HANDLED;
91 }
92 
93 static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
94 static DEFINE_PER_CPU(char [18], sibyte_hpt_name);
95 
sb1480_clockevent_init(void)96 void sb1480_clockevent_init(void)
97 {
98 	unsigned int cpu = smp_processor_id();
99 	unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu;
100 	struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
101 	unsigned char *name = per_cpu(sibyte_hpt_name, cpu);
102 	unsigned long flags =  IRQF_PERCPU | IRQF_TIMER;
103 
104 	BUG_ON(cpu > 3);	/* Only have 4 general purpose timers */
105 
106 	sprintf(name, "bcm1480-counter-%d", cpu);
107 	cd->name		= name;
108 	cd->features		= CLOCK_EVT_FEAT_PERIODIC |
109 				  CLOCK_EVT_FEAT_ONESHOT;
110 	clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
111 	cd->max_delta_ns	= clockevent_delta2ns(0x7fffff, cd);
112 	cd->max_delta_ticks	= 0x7fffff;
113 	cd->min_delta_ns	= clockevent_delta2ns(2, cd);
114 	cd->min_delta_ticks	= 2;
115 	cd->rating		= 200;
116 	cd->irq			= irq;
117 	cd->cpumask		= cpumask_of(cpu);
118 	cd->set_next_event	= sibyte_next_event;
119 	cd->set_state_shutdown	= sibyte_shutdown;
120 	cd->set_state_periodic	= sibyte_set_periodic;
121 	cd->set_state_oneshot	= sibyte_shutdown;
122 	clockevents_register_device(cd);
123 
124 	bcm1480_mask_irq(cpu, irq);
125 
126 	/*
127 	 * Map the timer interrupt to IP[4] of this cpu
128 	 */
129 	__raw_writeq(IMR_IP4_VAL,
130 		     IOADDR(A_BCM1480_IMR_REGISTER(cpu,
131 			R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (irq << 3)));
132 
133 	bcm1480_unmask_irq(cpu, irq);
134 
135 	irq_set_affinity(irq, cpumask_of(cpu));
136 	if (request_irq(irq, sibyte_counter_handler, flags, name, cd))
137 		pr_err("Failed to request irq %d (%s)\n", irq, name);
138 }
139