1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 1995, 1996, 2001 Ralf Baechle
4 * Copyright (C) 2001, 2004 MIPS Technologies, Inc.
5 * Copyright (C) 2004 Maciej W. Rozycki
6 */
7 #include <linux/delay.h>
8 #include <linux/kernel.h>
9 #include <linux/sched.h>
10 #include <linux/seq_file.h>
11 #include <asm/bootinfo.h>
12 #include <asm/cpu.h>
13 #include <asm/cpu-features.h>
14 #include <asm/idle.h>
15 #include <asm/mipsregs.h>
16 #include <asm/processor.h>
17 #include <asm/prom.h>
18
19 unsigned int vced_count, vcei_count;
20
21 /*
22 * No lock; only written during early bootup by CPU 0.
23 */
24 static RAW_NOTIFIER_HEAD(proc_cpuinfo_chain);
25
register_proc_cpuinfo_notifier(struct notifier_block * nb)26 int __ref register_proc_cpuinfo_notifier(struct notifier_block *nb)
27 {
28 return raw_notifier_chain_register(&proc_cpuinfo_chain, nb);
29 }
30
proc_cpuinfo_notifier_call_chain(unsigned long val,void * v)31 int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v)
32 {
33 return raw_notifier_call_chain(&proc_cpuinfo_chain, val, v);
34 }
35
show_cpuinfo(struct seq_file * m,void * v)36 static int show_cpuinfo(struct seq_file *m, void *v)
37 {
38 struct proc_cpuinfo_notifier_args proc_cpuinfo_notifier_args;
39 unsigned long n = (unsigned long) v - 1;
40 unsigned int version = cpu_data[n].processor_id;
41 unsigned int fp_vers = cpu_data[n].fpu_id;
42 char fmt[64];
43 int i;
44
45 #ifdef CONFIG_SMP
46 if (!cpu_online(n))
47 return 0;
48 #endif
49
50 /*
51 * For the first processor also print the system type
52 */
53 if (n == 0) {
54 seq_printf(m, "system type\t\t: %s\n", get_system_type());
55 if (mips_get_machine_name())
56 seq_printf(m, "machine\t\t\t: %s\n",
57 mips_get_machine_name());
58 }
59
60 seq_printf(m, "processor\t\t: %ld\n", n);
61 sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
62 cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : "");
63 seq_printf(m, fmt, __cpu_name[n],
64 (version >> 4) & 0x0f, version & 0x0f,
65 (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
66 seq_printf(m, "BogoMIPS\t\t: %u.%02u\n",
67 cpu_data[n].udelay_val / (500000/HZ),
68 (cpu_data[n].udelay_val / (5000/HZ)) % 100);
69 seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
70 seq_printf(m, "microsecond timers\t: %s\n",
71 cpu_has_counter ? "yes" : "no");
72 seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize);
73 seq_printf(m, "extra interrupt vector\t: %s\n",
74 cpu_has_divec ? "yes" : "no");
75 seq_printf(m, "hardware watchpoint\t: %s",
76 cpu_has_watch ? "yes, " : "no\n");
77 if (cpu_has_watch) {
78 seq_printf(m, "count: %d, address/irw mask: [",
79 cpu_data[n].watch_reg_count);
80 for (i = 0; i < cpu_data[n].watch_reg_count; i++)
81 seq_printf(m, "%s0x%04x", i ? ", " : "",
82 cpu_data[n].watch_reg_masks[i]);
83 seq_puts(m, "]\n");
84 }
85
86 seq_puts(m, "isa\t\t\t:");
87 if (cpu_has_mips_1)
88 seq_puts(m, " mips1");
89 if (cpu_has_mips_2)
90 seq_puts(m, " mips2");
91 if (cpu_has_mips_3)
92 seq_puts(m, " mips3");
93 if (cpu_has_mips_4)
94 seq_puts(m, " mips4");
95 if (cpu_has_mips_5)
96 seq_puts(m, " mips5");
97 if (cpu_has_mips32r1)
98 seq_puts(m, " mips32r1");
99 if (cpu_has_mips32r2)
100 seq_puts(m, " mips32r2");
101 if (cpu_has_mips32r5)
102 seq_puts(m, " mips32r5");
103 if (cpu_has_mips32r6)
104 seq_puts(m, " mips32r6");
105 if (cpu_has_mips64r1)
106 seq_puts(m, " mips64r1");
107 if (cpu_has_mips64r2)
108 seq_puts(m, " mips64r2");
109 if (cpu_has_mips64r5)
110 seq_puts(m, " mips64r5");
111 if (cpu_has_mips64r6)
112 seq_puts(m, " mips64r6");
113 seq_puts(m, "\n");
114
115 seq_puts(m, "ASEs implemented\t:");
116 if (cpu_has_mips16)
117 seq_puts(m, " mips16");
118 if (cpu_has_mips16e2)
119 seq_puts(m, " mips16e2");
120 if (cpu_has_mdmx)
121 seq_puts(m, " mdmx");
122 if (cpu_has_mips3d)
123 seq_puts(m, " mips3d");
124 if (cpu_has_smartmips)
125 seq_puts(m, " smartmips");
126 if (cpu_has_dsp)
127 seq_puts(m, " dsp");
128 if (cpu_has_dsp2)
129 seq_puts(m, " dsp2");
130 if (cpu_has_dsp3)
131 seq_puts(m, " dsp3");
132 if (cpu_has_mipsmt)
133 seq_puts(m, " mt");
134 if (cpu_has_mmips)
135 seq_puts(m, " micromips");
136 if (cpu_has_vz)
137 seq_puts(m, " vz");
138 if (cpu_has_msa)
139 seq_puts(m, " msa");
140 if (cpu_has_eva)
141 seq_puts(m, " eva");
142 if (cpu_has_htw)
143 seq_puts(m, " htw");
144 if (cpu_has_xpa)
145 seq_puts(m, " xpa");
146 if (cpu_has_loongson_mmi)
147 seq_puts(m, " loongson-mmi");
148 if (cpu_has_loongson_cam)
149 seq_puts(m, " loongson-cam");
150 if (cpu_has_loongson_ext)
151 seq_puts(m, " loongson-ext");
152 if (cpu_has_loongson_ext2)
153 seq_puts(m, " loongson-ext2");
154 seq_puts(m, "\n");
155
156 if (cpu_has_mmips) {
157 seq_printf(m, "micromips kernel\t: %s\n",
158 (read_c0_config3() & MIPS_CONF3_ISA_OE) ? "yes" : "no");
159 }
160
161 seq_puts(m, "Options implemented\t:");
162 if (cpu_has_tlb)
163 seq_puts(m, " tlb");
164 if (cpu_has_ftlb)
165 seq_puts(m, " ftlb");
166 if (cpu_has_tlbinv)
167 seq_puts(m, " tlbinv");
168 if (cpu_has_segments)
169 seq_puts(m, " segments");
170 if (cpu_has_rixiex)
171 seq_puts(m, " rixiex");
172 if (cpu_has_ldpte)
173 seq_puts(m, " ldpte");
174 if (cpu_has_maar)
175 seq_puts(m, " maar");
176 if (cpu_has_rw_llb)
177 seq_puts(m, " rw_llb");
178 if (cpu_has_4kex)
179 seq_puts(m, " 4kex");
180 if (cpu_has_3k_cache)
181 seq_puts(m, " 3k_cache");
182 if (cpu_has_4k_cache)
183 seq_puts(m, " 4k_cache");
184 if (cpu_has_tx39_cache)
185 seq_puts(m, " tx39_cache");
186 if (cpu_has_octeon_cache)
187 seq_puts(m, " octeon_cache");
188 if (raw_cpu_has_fpu)
189 seq_puts(m, " fpu");
190 if (cpu_has_32fpr)
191 seq_puts(m, " 32fpr");
192 if (cpu_has_cache_cdex_p)
193 seq_puts(m, " cache_cdex_p");
194 if (cpu_has_cache_cdex_s)
195 seq_puts(m, " cache_cdex_s");
196 if (cpu_has_prefetch)
197 seq_puts(m, " prefetch");
198 if (cpu_has_mcheck)
199 seq_puts(m, " mcheck");
200 if (cpu_has_ejtag)
201 seq_puts(m, " ejtag");
202 if (cpu_has_llsc)
203 seq_puts(m, " llsc");
204 if (cpu_has_guestctl0ext)
205 seq_puts(m, " guestctl0ext");
206 if (cpu_has_guestctl1)
207 seq_puts(m, " guestctl1");
208 if (cpu_has_guestctl2)
209 seq_puts(m, " guestctl2");
210 if (cpu_has_guestid)
211 seq_puts(m, " guestid");
212 if (cpu_has_drg)
213 seq_puts(m, " drg");
214 if (cpu_has_rixi)
215 seq_puts(m, " rixi");
216 if (cpu_has_lpa)
217 seq_puts(m, " lpa");
218 if (cpu_has_mvh)
219 seq_puts(m, " mvh");
220 if (cpu_has_vtag_icache)
221 seq_puts(m, " vtag_icache");
222 if (cpu_has_dc_aliases)
223 seq_puts(m, " dc_aliases");
224 if (cpu_has_ic_fills_f_dc)
225 seq_puts(m, " ic_fills_f_dc");
226 if (cpu_has_pindexed_dcache)
227 seq_puts(m, " pindexed_dcache");
228 if (cpu_has_userlocal)
229 seq_puts(m, " userlocal");
230 if (cpu_has_nofpuex)
231 seq_puts(m, " nofpuex");
232 if (cpu_has_vint)
233 seq_puts(m, " vint");
234 if (cpu_has_veic)
235 seq_puts(m, " veic");
236 if (cpu_has_inclusive_pcaches)
237 seq_puts(m, " inclusive_pcaches");
238 if (cpu_has_perf_cntr_intr_bit)
239 seq_puts(m, " perf_cntr_intr_bit");
240 if (cpu_has_ufr)
241 seq_puts(m, " ufr");
242 if (cpu_has_fre)
243 seq_puts(m, " fre");
244 if (cpu_has_cdmm)
245 seq_puts(m, " cdmm");
246 if (cpu_has_small_pages)
247 seq_puts(m, " small_pages");
248 if (cpu_has_nan_legacy)
249 seq_puts(m, " nan_legacy");
250 if (cpu_has_nan_2008)
251 seq_puts(m, " nan_2008");
252 if (cpu_has_ebase_wg)
253 seq_puts(m, " ebase_wg");
254 if (cpu_has_badinstr)
255 seq_puts(m, " badinstr");
256 if (cpu_has_badinstrp)
257 seq_puts(m, " badinstrp");
258 if (cpu_has_contextconfig)
259 seq_puts(m, " contextconfig");
260 if (cpu_has_perf)
261 seq_puts(m, " perf");
262 if (cpu_has_mac2008_only)
263 seq_puts(m, " mac2008_only");
264 if (cpu_has_ftlbparex)
265 seq_puts(m, " ftlbparex");
266 if (cpu_has_gsexcex)
267 seq_puts(m, " gsexcex");
268 if (cpu_has_shared_ftlb_ram)
269 seq_puts(m, " shared_ftlb_ram");
270 if (cpu_has_shared_ftlb_entries)
271 seq_puts(m, " shared_ftlb_entries");
272 if (cpu_has_mipsmt_pertccounters)
273 seq_puts(m, " mipsmt_pertccounters");
274 if (cpu_has_mmid)
275 seq_puts(m, " mmid");
276 if (cpu_has_mm_sysad)
277 seq_puts(m, " mm_sysad");
278 if (cpu_has_mm_full)
279 seq_puts(m, " mm_full");
280 seq_puts(m, "\n");
281
282 seq_printf(m, "shadow register sets\t: %d\n",
283 cpu_data[n].srsets);
284 seq_printf(m, "kscratch registers\t: %d\n",
285 hweight8(cpu_data[n].kscratch_mask));
286 seq_printf(m, "package\t\t\t: %d\n", cpu_data[n].package);
287 seq_printf(m, "core\t\t\t: %d\n", cpu_core(&cpu_data[n]));
288
289 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
290 if (cpu_has_mipsmt)
291 seq_printf(m, "VPE\t\t\t: %d\n", cpu_vpe_id(&cpu_data[n]));
292 else if (cpu_has_vp)
293 seq_printf(m, "VP\t\t\t: %d\n", cpu_vpe_id(&cpu_data[n]));
294 #endif
295
296 sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
297 cpu_has_vce ? "%u" : "not available");
298 seq_printf(m, fmt, 'D', vced_count);
299 seq_printf(m, fmt, 'I', vcei_count);
300
301 proc_cpuinfo_notifier_args.m = m;
302 proc_cpuinfo_notifier_args.n = n;
303
304 raw_notifier_call_chain(&proc_cpuinfo_chain, 0,
305 &proc_cpuinfo_notifier_args);
306
307 seq_puts(m, "\n");
308
309 return 0;
310 }
311
c_start(struct seq_file * m,loff_t * pos)312 static void *c_start(struct seq_file *m, loff_t *pos)
313 {
314 unsigned long i = *pos;
315
316 return i < NR_CPUS ? (void *) (i + 1) : NULL;
317 }
318
c_next(struct seq_file * m,void * v,loff_t * pos)319 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
320 {
321 ++*pos;
322 return c_start(m, pos);
323 }
324
c_stop(struct seq_file * m,void * v)325 static void c_stop(struct seq_file *m, void *v)
326 {
327 }
328
329 const struct seq_operations cpuinfo_op = {
330 .start = c_start,
331 .next = c_next,
332 .stop = c_stop,
333 .show = show_cpuinfo,
334 };
335