1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
4 */
5
6 #include <linux/clk.h>
7 #include <linux/interrupt.h>
8 #include <linux/sizes.h>
9 #include <asm/time.h>
10
11 #include <loongson1.h>
12 #include <platform.h>
13
14 #ifdef CONFIG_CEVT_CSRC_LS1X
15
16 #if defined(CONFIG_TIMER_USE_PWM1)
17 #define LS1X_TIMER_BASE LS1X_PWM1_BASE
18 #define LS1X_TIMER_IRQ LS1X_PWM1_IRQ
19
20 #elif defined(CONFIG_TIMER_USE_PWM2)
21 #define LS1X_TIMER_BASE LS1X_PWM2_BASE
22 #define LS1X_TIMER_IRQ LS1X_PWM2_IRQ
23
24 #elif defined(CONFIG_TIMER_USE_PWM3)
25 #define LS1X_TIMER_BASE LS1X_PWM3_BASE
26 #define LS1X_TIMER_IRQ LS1X_PWM3_IRQ
27
28 #else
29 #define LS1X_TIMER_BASE LS1X_PWM0_BASE
30 #define LS1X_TIMER_IRQ LS1X_PWM0_IRQ
31 #endif
32
33 DEFINE_RAW_SPINLOCK(ls1x_timer_lock);
34
35 static void __iomem *timer_reg_base;
36 static uint32_t ls1x_jiffies_per_tick;
37
ls1x_pwmtimer_set_period(uint32_t period)38 static inline void ls1x_pwmtimer_set_period(uint32_t period)
39 {
40 __raw_writel(period, timer_reg_base + PWM_HRC);
41 __raw_writel(period, timer_reg_base + PWM_LRC);
42 }
43
ls1x_pwmtimer_restart(void)44 static inline void ls1x_pwmtimer_restart(void)
45 {
46 __raw_writel(0x0, timer_reg_base + PWM_CNT);
47 __raw_writel(INT_EN | CNT_EN, timer_reg_base + PWM_CTRL);
48 }
49
ls1x_pwmtimer_init(void)50 void __init ls1x_pwmtimer_init(void)
51 {
52 timer_reg_base = ioremap(LS1X_TIMER_BASE, SZ_16);
53 if (!timer_reg_base)
54 panic("Failed to remap timer registers");
55
56 ls1x_jiffies_per_tick = DIV_ROUND_CLOSEST(mips_hpt_frequency, HZ);
57
58 ls1x_pwmtimer_set_period(ls1x_jiffies_per_tick);
59 ls1x_pwmtimer_restart();
60 }
61
ls1x_clocksource_read(struct clocksource * cs)62 static u64 ls1x_clocksource_read(struct clocksource *cs)
63 {
64 unsigned long flags;
65 int count;
66 u32 jifs;
67 static int old_count;
68 static u32 old_jifs;
69
70 raw_spin_lock_irqsave(&ls1x_timer_lock, flags);
71 /*
72 * Although our caller may have the read side of xtime_lock,
73 * this is now a seqlock, and we are cheating in this routine
74 * by having side effects on state that we cannot undo if
75 * there is a collision on the seqlock and our caller has to
76 * retry. (Namely, old_jifs and old_count.) So we must treat
77 * jiffies as volatile despite the lock. We read jiffies
78 * before latching the timer count to guarantee that although
79 * the jiffies value might be older than the count (that is,
80 * the counter may underflow between the last point where
81 * jiffies was incremented and the point where we latch the
82 * count), it cannot be newer.
83 */
84 jifs = jiffies;
85 /* read the count */
86 count = __raw_readl(timer_reg_base + PWM_CNT);
87
88 /*
89 * It's possible for count to appear to go the wrong way for this
90 * reason:
91 *
92 * The timer counter underflows, but we haven't handled the resulting
93 * interrupt and incremented jiffies yet.
94 *
95 * Previous attempts to handle these cases intelligently were buggy, so
96 * we just do the simple thing now.
97 */
98 if (count < old_count && jifs == old_jifs)
99 count = old_count;
100
101 old_count = count;
102 old_jifs = jifs;
103
104 raw_spin_unlock_irqrestore(&ls1x_timer_lock, flags);
105
106 return (u64) (jifs * ls1x_jiffies_per_tick) + count;
107 }
108
109 static struct clocksource ls1x_clocksource = {
110 .name = "ls1x-pwmtimer",
111 .read = ls1x_clocksource_read,
112 .mask = CLOCKSOURCE_MASK(24),
113 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
114 };
115
ls1x_clockevent_isr(int irq,void * devid)116 static irqreturn_t ls1x_clockevent_isr(int irq, void *devid)
117 {
118 struct clock_event_device *cd = devid;
119
120 ls1x_pwmtimer_restart();
121 cd->event_handler(cd);
122
123 return IRQ_HANDLED;
124 }
125
ls1x_clockevent_set_state_periodic(struct clock_event_device * cd)126 static int ls1x_clockevent_set_state_periodic(struct clock_event_device *cd)
127 {
128 raw_spin_lock(&ls1x_timer_lock);
129 ls1x_pwmtimer_set_period(ls1x_jiffies_per_tick);
130 ls1x_pwmtimer_restart();
131 __raw_writel(INT_EN | CNT_EN, timer_reg_base + PWM_CTRL);
132 raw_spin_unlock(&ls1x_timer_lock);
133
134 return 0;
135 }
136
ls1x_clockevent_tick_resume(struct clock_event_device * cd)137 static int ls1x_clockevent_tick_resume(struct clock_event_device *cd)
138 {
139 raw_spin_lock(&ls1x_timer_lock);
140 __raw_writel(INT_EN | CNT_EN, timer_reg_base + PWM_CTRL);
141 raw_spin_unlock(&ls1x_timer_lock);
142
143 return 0;
144 }
145
ls1x_clockevent_set_state_shutdown(struct clock_event_device * cd)146 static int ls1x_clockevent_set_state_shutdown(struct clock_event_device *cd)
147 {
148 raw_spin_lock(&ls1x_timer_lock);
149 __raw_writel(__raw_readl(timer_reg_base + PWM_CTRL) & ~CNT_EN,
150 timer_reg_base + PWM_CTRL);
151 raw_spin_unlock(&ls1x_timer_lock);
152
153 return 0;
154 }
155
ls1x_clockevent_set_next(unsigned long evt,struct clock_event_device * cd)156 static int ls1x_clockevent_set_next(unsigned long evt,
157 struct clock_event_device *cd)
158 {
159 raw_spin_lock(&ls1x_timer_lock);
160 ls1x_pwmtimer_set_period(evt);
161 ls1x_pwmtimer_restart();
162 raw_spin_unlock(&ls1x_timer_lock);
163
164 return 0;
165 }
166
167 static struct clock_event_device ls1x_clockevent = {
168 .name = "ls1x-pwmtimer",
169 .features = CLOCK_EVT_FEAT_PERIODIC,
170 .rating = 300,
171 .irq = LS1X_TIMER_IRQ,
172 .set_next_event = ls1x_clockevent_set_next,
173 .set_state_shutdown = ls1x_clockevent_set_state_shutdown,
174 .set_state_periodic = ls1x_clockevent_set_state_periodic,
175 .set_state_oneshot = ls1x_clockevent_set_state_shutdown,
176 .tick_resume = ls1x_clockevent_tick_resume,
177 };
178
ls1x_time_init(void)179 static void __init ls1x_time_init(void)
180 {
181 struct clock_event_device *cd = &ls1x_clockevent;
182 int ret;
183
184 if (!mips_hpt_frequency)
185 panic("Invalid timer clock rate");
186
187 ls1x_pwmtimer_init();
188
189 clockevent_set_clock(cd, mips_hpt_frequency);
190 cd->max_delta_ns = clockevent_delta2ns(0xffffff, cd);
191 cd->max_delta_ticks = 0xffffff;
192 cd->min_delta_ns = clockevent_delta2ns(0x000300, cd);
193 cd->min_delta_ticks = 0x000300;
194 cd->cpumask = cpumask_of(smp_processor_id());
195 clockevents_register_device(cd);
196
197 ls1x_clocksource.rating = 200 + mips_hpt_frequency / 10000000;
198 ret = clocksource_register_hz(&ls1x_clocksource, mips_hpt_frequency);
199 if (ret)
200 panic(KERN_ERR "Failed to register clocksource: %d\n", ret);
201
202 if (request_irq(LS1X_TIMER_IRQ, ls1x_clockevent_isr,
203 IRQF_PERCPU | IRQF_TIMER, "ls1x-pwmtimer",
204 &ls1x_clockevent))
205 pr_err("Failed to register ls1x-pwmtimer interrupt\n");
206 }
207 #endif /* CONFIG_CEVT_CSRC_LS1X */
208
plat_time_init(void)209 void __init plat_time_init(void)
210 {
211 struct clk *clk = NULL;
212
213 /* initialize LS1X clocks */
214 ls1x_clk_init();
215
216 #ifdef CONFIG_CEVT_CSRC_LS1X
217 /* setup LS1X PWM timer */
218 clk = clk_get(NULL, "ls1x-pwmtimer");
219 if (IS_ERR(clk))
220 panic("unable to get timer clock, err=%ld", PTR_ERR(clk));
221
222 mips_hpt_frequency = clk_get_rate(clk);
223 ls1x_time_init();
224 #else
225 /* setup mips r4k timer */
226 clk = clk_get(NULL, "cpu_clk");
227 if (IS_ERR(clk))
228 panic("unable to get cpu clock, err=%ld", PTR_ERR(clk));
229
230 mips_hpt_frequency = clk_get_rate(clk) / 2;
231 #endif /* CONFIG_CEVT_CSRC_LS1X */
232 }
233